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Si3215
PRO SLIC (R) PROGRAMMABLE CMOS SLIC/C O D E C W I T H RI N G I N G / BA T T E R Y VO L TA G E G E N E R A T I O N
Features
Performs all BORSCHT functions Software-programmable internal balanced ringing up to 90 VPK (5 REN up to 4 kft, 3 REN up to 8 kft) Integrated battery supply with dynamic voltage output On-chip dc-dc converter continuously minimizes power in all operating modes Entire solution can be powered from a single 3.3 V or 5 V supply 3.3 to 35 V dc input range Dynamic 0 to -94.5 V output Low-cost inductor and high-efficiency transformer versions supported Software-programmable linefeed parameters: Ringing frequency, amplitude, cadence, and waveshape 2-wire ac impedance and hybrid Constant current feed (20 to 41 mA) Loop closure and ring trip thresholds and filtering Software-programmable signal generation and audio processing: Phase-continuous FSK (caller ID) generation Dual audio tone generators Smooth and abrupt polarity reversal -Law/A-Law and 16-bit linear PCM audio Extensive test and diagnostic features Multiple voice loopback test modes Real time dc linefeed measurement GR-909 line test capabilities SPI and PCM bus digital interfaces Extensive programmable interrupts 100% software-configurable global solution Ideal for customer premise equipment applications Lead-free and RoHS-compliant packages available
Ordering Information See page 111.
Pin Assignments
Si3215
QFN
DRX PCLK INT CS SCLK SDI SDO
Applications
Voice-over-broadband systems: DSL, cable, wireless PBX/IP-PBX/key telephone systems Terminal adapters: ISDN, Ethernet, USB
Description
The ProSLIC is a low-voltage CMOS device that provides a complete analog telephone interface ideal for customer premise equipment (CPE) applications. The ProSLIC integrates subscriber line interface circuit (SLIC), codec, and battery generation functionality into a single CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3215M only) or 5 V supply. The ProSLIC controls the phone line through Silicon Labs' Si3201 Linefeed Interface Chip or discrete component line feed. Si3215 features include software-configurable 5 REN internal ringing up to 90 VPK, DTMF generation, and a comprehensive set of telephony signaling capabilities including expanded support of Japan and China country requirements. The ProSLIC is packaged in a 38-pin QFN and TSSOP, and the Si3201 is packaged in a thermally-enhanced 16pin SOIC.
DTX FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC
1 38 37 36 35 34 33 32 31 30 2 3 4 5 6 7 8 9 10 11 29 28 27 26 25 24 23 22 21
12 13 14 15 16 17 18 19 20
SDITHRU DCDRV DCFF TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP
U.S. Patent #6,567,521 U.S. Patent #6,812,744 Other patents pending
Functional Block Diagram
INT CS SCLK SDO SDI DTX RESET
Si3215
Line Status
Control Interface Compression Gain/ Attenuation/ Filter Tone Generators Gain/ Attenuation/ Filter D/A A/D Line Feed Control TIP Prog. Hybrid Linefeed Interface RING ZS
DRX
PCM Interface
FSYNC PCLK PLL
Expansion
DC-DC Converter Controller
Discrete Components
Rev. 0.92 8/05
Copyright (c) 2005 by Silicon Laboratories
STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA
Si3215
Si3215
2
Rev. 0.92
Si3215 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1. Si3210 to Si3215 Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.7. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.11. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.12. Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.1. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.3. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.4. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5. Pin Descriptions: Si3215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Rev. 0.92
3
Si3215
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage Operating Temperature Range2 Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical Continuous Power Dissipation2 Si3201 DC Supply Voltage Battery Supply Voltage Input Voltage: TIP, RING, SRINGE, STIPE pins Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins Operating Temperature Range2 Storage Temperature Range SOIC-16 Thermal Resistance, Typical3 Continuous Power Dissipation2 VDD VBAT VINHV VIN TA TSTG JA PD -0.5 to 6.0 -104 (VBAT - 0.3) to (VDD + 0.3) -0.3 to (VDD + 0.3) -40 to 100 -40 to 150 55 0.8 at 70 C 0.6 at 85 oC
o
Symbol Si3215 VDDD, VDDA1, VDDA2 IIN VIND TA TSTG JA JA PD
Value -0.5 to 6.0 10 -0.3 to (VDDD + 0.3) -40 to 100 -40 to 150 70 35 0.7
Unit V mA V C C C/W C/W W V V V V C C C/W W
Notes: 1. Permanent device damage may occur if these absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Operation above 125 oC junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
4
Rev. 0.92
Si3215
Table 2. Recommended Operating Conditions
Parameter Ambient Temperature Ambient Temperature Si3215 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage Symbol TA TA VDDD,VDDA1, VDDA2 VDD VBAT VBATH = VBAT Test Condition K-grade B-grade Min* 0 -40 3.13 3.13 -96 Typ 25 25 3.3/5.0 3.3/5.0 -- Max* 70 85 5.25 5.25 -10 Unit
oC o
C
V V V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated. Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used.
Table 3. AC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter Overload Level Single Frequency Distortion
1
Test Condition TX/RX Performance THD = 1.5% 2-wire - PCM or PCM - 2-wire: 200 Hz-3.4 kHz 200 Hz to 3.4 kHz D/A or A/D 8-bit Active off-hook, and OHT, any ZAC 0 dBm0, Active off-hook, and OHT, any Zac 2-wire to PCM, 1014 Hz PCM to 2-wire, 1014 Hz
Min 2.5 --
Typ -- --
Max -- -45
Unit VPK dB
Signal-to-(Noise + Distortion) Ratio2
Figure 1
--
--
Audio Tone Generator Signal-to-Distortion Ratio2 Intermodulation Distortion Gain Accuracy
2
45 -- -0.5 -0.5 Figure 3,4 Figure 5,6
-- -- 0 0 -- --
-- -45 0.5 0.5 -- --
dB dB dB dB
Gain Accuracy Over Frequency Group Delay Over Frequency Gain Tracking3 1014 Hz sine wave, reference level -10 dBm signal level: 3 dB to -37 dB -37 dB to -50 dB -50 dB to -60 dB Round-Trip Group Delay Gain Step Accuracy Gain Variation with Temperature Gain Variation with Supply at 1000 Hz -6 dB to 6 dB All gain settings VDDA = VDDA = 3.3/5 V 5%
-0.25 -0.5 -1.0 -- -0.017 -0.25 -0.1
-- -- -- 1100 -- -- --
0.25 0.5 1.0 -- 0.017 0.25 0.1
dB dB dB s dB dB dB
Rev. 0.92
5
Si3215
Table 3. AC Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter 2-Wire Return Loss Transhybrid Balance Idle Channel Noise4
Test Condition 200 Hz to 3.4 kHz 300 Hz to 3.4 kHz Noise Performance C-Message Weighted Psophometric Weighted 3 kHz flat
Min 30 30 -- -- -- 40 40 40 56 43 53 53 40
Typ 35 -- -- -- -- -- -- -- 60 60 60 60 --
Max -- -- 15 -75 18 -- -- -- -- -- -- -- --
Unit dB dB dBrnC dBmP dBrn dB dB dB dB dB dB dB dB
PSRR from VDDA PSRR from VDDD PSRR from VBAT Longitudinal to Metallic or PCM Balance
RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz Longitudinal Performance 200 Hz to 3.4 kHz, Q1,Q2 150, 1% mismatch Q1,Q2 = 60 to 2405 Q1,Q2 = 300 to 800 Using Si3201
5
Metallic to Longitudinal Balance Longitudinal Impedance
200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register selectable
ETBO/ETBA
00 01 10 Longitudinal Current per Pin Active off-hook 200 Hz to 3.4 kHz Register selectable
ETBO/ETBA
-- -- --
33 17 17
-- -- --

00 01 10
-- -- --
4 8 8
-- -- --
mA mA mA
Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be -10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the 3/A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 dB to -37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed -55 dBm. 5. Assumes normal distribution of betas.
6
Rev. 0.92
Si3215
Figure 1. Transmit and Receive Path SNDR
9 8 7 6
Fundamental Output Power 5 (dBm0) Acceptable Region
4 3
2.6
2 1 0 1 2 3 4 5 6 7 8 9
Fundamental Input Power (dBm0)
Figure 2. Overload Compression Performance
Rev. 0.92
7
Si3215
Typical Response
Typical Response
Figure 3. Transmit Path Frequency Response
8
Rev. 0.92
Si3215
Figure 4. Receive Path Frequency Response
Rev. 0.92
9
Si3215
Figure 5. Transmit Group Delay Distortion
Figure 6. Receive Group Delay Distortion
10
Rev. 0.92
Si3215
Table 4. Linefeed Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85 C for B-Grade)
Parameter Loop Resistance Range DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance DC Open Circuit Voltage-- Ground Start DC Output Resistance-- Ground Start DC Output Resistance-- Ground Start Loop Closure/Ring Ground Detect Threshold Accuracy Ring Trip Threshold Accuracy Ring Trip Response Time Ring Amplitude Ring DC Offset Trapezoidal Ring Crest Factor Accuracy Sinusoidal Ring Crest Factor Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Power Alarm Threshold Accuracy
Symbol RLOOP
Test Condition See note. ILIM = 29 mA, ETBA = 4 mA Active Mode; VOC = 48 V, VTIP - VRING
Min 0 -10 -4 -- -4 -- 150 -20 -10 -- 44 0 -.05 1.35
Typ -- -- -- 160 -- 160 -- -- -- -- -- -- -- -- -- -- -- --
Max 160 10 4 -- 4 -- -- 20 10 -- -- -- .05 1.45 1 50 600 25
Unit % V V k % %
RDO VOCTO RROTO RTOTO
ILOOP < ILIM IRINGVTR ROS
5 REN load; sine wave; RLOOP = 160 , VBAT = -75 V Programmable in Indirect Register 6 Crest factor = 1.3
Vrms V
RCF f = 20 Hz Accuracy of ON/OFF Times CAL to CAL Bit At Power Threshold = 300 mW
-1 -50 -- -25
% ms ms %
Note: DC resistance round trip; 160 corresponds to 2 kft 26 gauge AWG.
Rev. 0.92
11
Si3215
Table 5. Monitor ADC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter Differential Nonlinearity (6-bit resolution) Integral Nonlinearity (6-bit resolution) Gain Error (voltage) Gain Error (current)
Symbol DNLE INLE
Test Condition
Min -1/2 -1 -- --
Typ -- -- -- --
Max 1/2 1 10 20
Unit LSB LSB % %
Table 6. Si321x DC Characteristics, VDDA = VDDD = 5.0 V
(VDDA, VDDD = 4.75 to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage
Symbol VIH VIL VOH
Test Condition
Min 0.7 x VDDD --
Typ -- -- -- -- --
Max -- 0.3 x VDD
D
Unit V V V V V
SDITHRU:IO = -4 mA SDO, DTX:IO = -8 mA DOUT: IO = -40 mA
VDDD - 0.6 VDDD - 0.8 --
-- -- 0.4
Low Level Output Voltage
VOL
SDITHRU: IO = 4 mA SDO,INT,DTX:IO = 8 mA
Input Leakage Current
IL
-10
--
10
A
Table 7. Si321x DC Characteristics, VDDA = VDDD = 3.3 V
(VDDA, VDDD = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage
Symbol VIH VIL VOH
Test Condition
Min 0.7 x VDDD --
Typ -- -- -- -- --
Max -- 0.3 x VDD
D
Unit V V V V V
SDITHRU: IO =-2 mA SDO, DTX:IO = -4 mA DOUT: IO = -40 mA
VDDD - 0.6 VDDD - 0.8 --
-- -- 0.4
Low Level Output Voltage
VOL
SDITHRU: IO = 2 mA SDO,INT,DTX:IO = 4 mA
Input Leakage Current
IL
-10
--
10
A
12
Rev. 0.92
Si3215
Table 8. Power Supply Characteristics
(VDDA, VDDD = 3.13 V to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter Power Supply Current, Analog and Digital
Symbol IA + ID
Test Condition Sleep (RESET = 0) Open Active on-hook ETBO = 4 mA, codec and Gm amplifier powered down Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA, ILIM = 20 mA Ground-start Ringing Sinewave, REN = 1, VPK = 56 V
Typ1 0.1 33 37
Typ2 0.13 42.8 53
Max 0.3 49 68
Unit mA mA mA
57 73 36 45 -- -- -- -- -- -- -- -- -- -- -- -- --
72 88 47 55 100 100 110 1 1 0 0 3 11 30 2 5.5 --
83 99 55 65 -- -- -- -- -- -- -- -- -- -- -- -- 10
mA mA mA mA A A A mA mA mA mA mA mA mA mA mA V/s
VDD Supply Current (Si3201)
IVDD
Sleep mode, RESET = 0 Open (high impedance) Active on-hook standby Forward/reverse active off-hook, no ILOOP, ETBO = 4 mA, VBAT = -24 V Forward/reverse OHT, ETBO = 4 mA, VBAT = -70 V
VBAT Supply Current3
IBAT
Sleep (RESET = 0) Open (DCOF = 1) Active on-hook VOC = 48 V, ETBO = 4 mA Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA, ILIM = 20 mA Ground-start Ringing VPK_RING = 56 VPK, sinewave ringing, REN = 1
VBAT Supply Slew Rate
When using Si3201
Notes: 1. VDDD, VDDA = 3.3 V. 2. VDDD, VDDA = 5.25 V. 3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supply regulator efficiency of 71%, the user can calculate the regulator current consumption as IBAT x VBAT/(0.71 x VDC).
Rev. 0.92
13
Si3215
Table 9. Switching Characteristics--General Inputs
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade, CL = 20 pF)
Parameter Rise Time, RESET RESET Pulse Width
Symbol tr trl
Min -- 100
Typ -- --
Max 20 --
Unit ns ns
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
Table 10. Switching Characteristics--SPI
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade, CL = 20 pF
Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active Delay Time, SCLK Fall to SDO Transition Delay Time, CS Rise to SDO Tri-state Setup Time, CS to SCLK Fall Hold Time, CS to SCLK Rise Setup Time, SDI to SCLK Rise Hold Time, SDI to SCLK Rise Delay Time between Chip Selects (Continuous SCLK) Delay Time between Chip Selects (Non-continuous SCLK) SDI to SDITHRU Propagation Delay
Symbol tc tr tf td1 td2 td3 tsu1 th1 tsu2 th2 tcs tcs td4
Test Conditions
Min 0.062 -- -- -- -- -- 25 20 25 20 440 220 --
Typ -- -- -- -- -- -- -- -- -- -- -- -- 4
Max -- 25 25 20 20 20 -- -- -- -- -- -- 10
Unit s ns ns ns ns ns ns ns ns ns ns ns ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD -0.4 V, VIL = 0.4 V
14
Rev. 0.92
Si3215
tr tthru tc tr
SCLK
tsu1
th1 tcs tsu2 th2
CS
SDI
td1 td2 td3
SDO
Figure 7. SPI Timing Diagram
Table 11. Switching Characteristics--PCM Highway Serial Interface
VD = 3.13 to 5.25 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade, CL = 20 pF
Parameter PCLK Frequency
Symbol 1/tc
Test Conditions
Min 1 -- -- -- -- -- -- -- -- 40 -120 -- -- -- -- -- 25 20 25 20
Typ 1 0.256 0.512 0.768 1.024 1.536 2.048 4.096 8.192 50 -- -- -- -- -- -- -- -- -- --
Max 1 -- -- -- -- -- -- -- -- 60 120 25 25 20 20 20 -- -- -- --
Units MHz MHz MHz MHz MHz MHz MHz MHz % ns ns ns ns ns ns ns ns ns ns
PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Delay Time, PCLK Rise to DTX Active Delay Time, PCLK Rise to DTX Transition Delay Time, PCLK Rise to DTX Tri-State2 Setup Time, FSYNC to PCLK Fall Hold Time, FSYNC to PCLK Fall Setup Time, DRX to PCLK Fall Hold Time, DRX to PCLK Fall
tdty tjitter tr tf td1 td2 td3 tsu1 th1 tsu2 th2
Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VI/O -0.4 V, VIL = 0.4 V 2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
Rev. 0.92
15
Si3215
tc PCLK tsu1 FSYNC tsu2 DRX td1 DTX
Figure 8. PCM Highway Interface Timing Diagram
VCC
tr
tf
th1
th2
td2
td3
32
31
23
10
27
GNDA
TEST
VDDA1
VDDA2
GNDD
R1 2 0 0k 15 C24 0 .1 F 20 C3 220 nF R8 4 .7 k
STIPDC STIPAC
VDDD
30
SCLK SDI SD O CS
38 37 36 1
VCC
SPI Bus
8
7
GND
VDD
C18 4 .7 F
C19 4 .7 F
FSYN C
6 3 4 5
Si3215/Si3215M
ITIPN IRIN GN
15 13 16 14 11 10 R7 4 .0 2 k R2 1 9 6k R4 1 9 6k
29 25 28 26 17 19
ITIPN IR ING N ITIPP IR ING P STIPE SRIN G E
PCLK D RX DTX
PCM Bus
VCC R322 1 0k
Si3201
TIP
P ro t ec t io n C irc u it
1 C5 22 n F C6 22 n F 3
4
TIP
ITIPP IRING P STIPE SRING E
IN T RESET IG M P IG M N
2 7 Note 2 R262 40 .2 k
RING
R ING
24 22 R15 243
R6 4 .0 2 k 18 R5 2 0 0k
VBATH
VBAT
SVBAT IR EF C APP CAPM QGN D
11 12 14 C2 10 F C1 10 F R14 4 0 .2k
C4 220 nF
R9 4 .7 k
5
4
21 16
SR ING AC DCDRV SR ING DC SDCH SDCL
N otes: 1. V a lues a nd config urations for th ese com p onen ts can b e d erived from T ab le 19 or fro m "A N 45: D e sign G uide for the S i 321 0 D C D C C o nverter" . 2. O nly on e com pone nt pe r system nee ded . 3. A ll circuit gro und shou ld h ave a sing le -po int conn ection to the gro und plan e . 4. S i3 201 botto m -sid e exposed pa d sho uld be electrica lly a nd th erm a lly con nected to bu lk gro und pla ne .
R21 15 R29
1
13
C26 0 .1 F
9
8
34
33
GND Q9 2N 2 2 2 2 R28
1
DCFF
R3 2 0 0k
L2 VDDA1 VDDA2 47 H C31 10 F 10 V C15 0.1 F C16 C17 0.1 F 0.1 F
VDDD C30 10 F
SDCH
SDCL
DCFF
VCC
DCDRV
VDC VDC
N o te 1
VBAT D C -D C C o n v e rt e r C irc u it
Figure 9. Si3215/Si3215M Application Circuit Using Si3201
16
Rev. 0.92
Si3215
Table 12. Si3215/Si3215M External Component Values
Component(s)
C1,C2 C3,C4 C5,C6 C15,C16,C17,C24 C18,C19 C26 C30, C31 L2 R1,R3,R5 R2,R4 R6,R7 R8,R9 R14,R26* R15 R21 R28,R29 R32* Q9
Value
10 F, 6 V Ceramic or 16 V Low Leakage Electrolytic, 20% 220 nF, 100 V, X7R, 20% 22 nF, 100 V, X7R, 20% 0.1 F, 6 V, Y5V, 20% 4.7 F Ceramic, 6 V, X7R, 20% 0.1 F, 100 V, X7R, 20% 10 F, 6 V, Electrolytic, 20% 47 H, 150 A 200 k, 1/10 W, 1% 196 k, 1/10 W, 1% 4.02 k, 1/10 W, 1% 4.7 k, 1/10 W, 1% 40.2 k, 1/10 W, 1% 243 , 1/10 W, 1% 15 , 1/4 W, 5% 1/10 W, 1% (See AN45 or Table 17 for value selection) 10 k, 1/10 W, 5% 60 V, General Purpose Switching NPN
Supplier
Murata, Nichicon URL1C100MD Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic Coilcraft
ON Semi MMBT2222ALT1; Central Semi CMPT2222A; Zetex FMMT2222
*Note: Only one component per system needed.
VDC
F1
SDCH R191
See Note 1
SDCL R201
R181
C252 10 F
C142 0.1 F
Si3215
C10 0.1 F
R16 200 Q7 FZT953
DCFF
Q8 2N2222
D1 ES1D C9 10 F
VBAT
R17 L1 DCDRV
See Note 1 Notes: 1. Values and configurations for these components can be derived from Table 21 or from "AN45: Design Guide for the Si3210 DC-DC Converter". 2. Voltage rating for C14 and C25 must be greater than VDC.
GND
Figure 10. Si3215 BJT/Inductor DC-DC Converter Circuit
Rev. 0.92
17
Si3215
Table 13. Si3215 BJT/Inductor DC-DC Converter Component Values
Component(s) Value Supplier
C9 C10 C141 C25
1
10 F, 100 V, Electrolytic, 20% 0.1 F, 50 V, X7R, 20% 0.1 F, X7R, 20% 10 F, Electrolytic, 20% 200 , 1/10 W, 5% 1/10 W, 5% (See AN452 or Table 19 for value selection) 1/4 W, 5% (See AN45 or Table 19 for value selection) 1/10 W, 1% (See AN45 or Table 19 for value selection) Fuse Ultra Fast Recovery 200 V, 1 A Rectifier 1A, Shielded Inductor (See "AN45: Design Guide for the Si3210 DC-DC Converter" or Table 19 for value selection) 120 V, High Current Switching PNP 60 V, General Purpose Switching NPN
Panasonic Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic
R16 R17 R18 R19,R20 F1 D1 L1
Belfuse SSQ Series General Semi ES1D; Central Semi CMR1U-02 API Delevan SPD127 series, Sumida CDRH127 series, Datatronics DR340-1 series, Coilcraft DS5022, TDK SLF12565 Zetex FZT953, FZT955, ZTX953, ZTX955; Sanyo 2SA1552 ON Semi MMBT2222ALT1, MPS2222A; Central Semi CMPT2222A; Zetex FMMT2222
Q7 Q8
Notes: 1. Voltage rating of this device must be greater than VDC. 2. "AN45: Design Guide for the Si3210 DC-DC Converter".
18
Rev. 0.92
Si3215
VDC
F1
SDCH R191
Note 1
SDCL R201
R181
C252 10uF
C142 0.1uF
Si3215M
1 C27 470pF DCFF M1 IRLL014N R22 22 2 3 4 6 10 D1 ES1D C9 10uF VBAT
T11
Note 1
R17 200k DCDRV NC
GND
Notes: 1. Values and configurations for these components can be derived from Table 20 or from "AN45: Design Guide for the Si3210 DC-DC Converter". 2. Voltage rating for C14 and C25 must be greater than VDC.
Figure 11. Si3215M MOSFET/Transformer DC-DC Converter Circuit
Table 14. Si3215M MOSFET/Transformer DC-DC Converter Component Values
Component(s) C9 C141 C251 C27 R17 R18 R19,R20 Value 10 F, 100 V, Electrolytic, 20% 0.1 F, X7R, 20% 10 F, Electrolytic, 20% 470 pF, 100 V, X7R, 20% 200 k, 1/10 W, 5% 1/4 W, 5% (See AN452 or Table 18 for value selection) 1/10 W, 1% (See AN45 or Table 18 for value selection) 22 , 1/10 W, 5% Fuse Ultra Fast Recovery 200 V, 1A Rectifier Supplier Panasonic Murata, Johanson, Novacap, Venkel Panasonic Murata, Johanson, Novacap, Venkel
R22 F1 D1 T1
Power Transformer
M1
100 V, Logic Level Input MOSFET
Belfuse SSQ Series General Semi ES1D; Central Semi CMR1U-02 Coiltronic CTX01-15275; Datatronics SM76315; Midcom 31353R-02 Intl Rect. IRLL014N; Intersil HUF76609D3S; ST Micro STD5NE10L, STN2NE10L
Notes: 1. Voltage rating of this device must be greater than VDC. 2. "AN45: Design Guide for the Si3210 DC-DC Converter".
Rev. 0.92
19
Si3215
VCC
32
31
23
10
27
GND
GNDD
GNDA
VDDA1
VDDA2
R1 200k GND
VDDD
TEST
30
15 20
SCLK STIPDC STIPAC SDI SDO CS FSYNC ITIPP
38 37 36 1
SPI Bus
C3 220nF
R8 4.7k
6 3 4 5
Q1 5401
29
C32 4 0.1 F
TIP
Protection Circuit C5 22nF C6 22nF
Q6 5551
ITIPN STIPE
Si3215/Si3215M
R10 10 C8 220nF R6 80.6
Q4 5401
28
PCLK DRX DTX
PCM Bus
VCC R322 10k
R13 5.1k
R102 (100k)
17 R2 100k 26
IRINGP IRINGN SRINGE
INT RESET IGMP IGMN
2 7 Note 2 R262 40.2k
RING
Q2 5401 Q5 5551
R11 10 C7 220nF R7 80.6
Q3 5401
C34 4 0.1 F R104 (100k)
25 R4 100k 19
24 22 R15 243
R12 5.1k
C33 4 0.1 F R105 (100k)
R5 100k
18
SVBAT
IREF CAPP CAPM QGND DCFF
11 12 14 C2 10uF C1 10uF R14 40.2k
C4 220nF
R9 4.7k
Notes: 1. Values and configurations for these components can be derived from Table 19 or from "AN45: Design Guide for the Si3210 DCDC Converter". 2. Only one component per system needed. 3. All circuit grounds should have a single-point connection to the ground plane. 4. Optional components to improve idle channel noise
21 16
SRINGAC DCDRV SRINGDC SDCH SDCL
13
C26 0.1uF R21 15 Q9 2N2222
GND
R3 200k
L2 V DDA1 V DDA 2 4 7 H
34
33
9
8
V DDD
DCDRV
SDCH
VCC SDCL R29
1
R28
1
DCFF
VDC
Note 1
VBAT
C3 1 1 0 F 10 V
C1 5 0 .1 F
C1 6 C1 7 0 .1 F 0. 1 F
C3 0 10 F
DC-DC Converter Circuit
VDC
Figure 12. Si3215/Si3215M Typical Application Circuit Using Discrete Components
Table 15. Si3215/Si3215M External Component Values--Discrete Solution
Component Value Supplier/Part Number
C1,C2 C3,C4 C5,C6 C7,C8 C15,C16,C17 C26 C30, C31 L2 Q1,Q2,Q3,Q4
10 F, 6 V Ceramic or 16 V Low Leakage Electrolytic, 20% 220 nF, 100 V, X7R, 20% 22 nF, 100 V, X7R, 20% 220 nF, 50 V, X7R, 20% 0.1 F, 6 V, Y5V, 20% 0.1 F, 100 V, X7R, 20% 10 F, 16 V, Electrolytic, 20% 47 H, 150 A 120 V, PNP, BJT
Murata, Panasonic, Nichicon URL1C100MD Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic Coilcraft Central Semi CMPT5401; ON Semi MMBT5401LT1, 2N5401; Zetex FMMT5401; Fairchild 2N5401; Samsung 2N5410 Central Semi CZT5551, ON Semi 2N5551; Fairchild 2N5551; Phillips 2N5551
Q5,Q6
120 V, NPN, BJT
20
Rev. 0.92
Si3215
Table 15. Si3215/Si3215M External Component Values--Discrete Solution (Continued)
Q9 NPN General Purpose BJT ON Semi MMBT2222ALT1, MPS2222A; Central Semi CMPT2222A; Zetex FMMT2222
R1,R3 R2,R4,R5, R102,R104, R105 R6,R7 R8,R9 R10,R11 R12,R13 R14,R26* R15 R21 R28,R29 R32*
200 k, 1/10 W, 1% 100 k, 1/10 W, 1% 80.6 , 1/4 W, 1% 4.7 k, 1/10 W, 1% 10 , 1/10 W, 5% 5.1 k, 1/10 W, 5% 40.2 k, 1/10 W, 1% 243 , 1/10 W, 1% 15 , 1/4 W, 1% 1/10 W, 1% (See AN45 or Table 17 for value selection) 10 k, 1/10 W, 5%
Note: Only one component per system needed.
QRDN Q3 5401 Q4
QTDN 5401
R23 RRBN0 3.0k QRP Q5 5551 C7 CRBN 100 nF R6 RTE 80.6 Q6 5551 QTN
R24 RTBN0 3.0k
C8 CTBN 100 nF
R7 RRE 80.6
R12 RRBN 5.1k
R13 RTBN 5.1k
Figure 13. Si321x Optional Equivalent Q5, Q6 Bias Circuit3
Rev. 0.92
21
Si3215
The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5, Q6. For this optional subcircuit, C7 and C8 are different in voltage and capacitance than the standard circuit. R23 and R24 are additional components.
Table 16. Si321x Optional Bias Component Values
Component C7,C8 R23,R24 Value 100 nF, 100 V, X7R, 20% 3.0 k, 1/10 W, 5% Supplier/Part Number Murata, Johanson, Venkel
Table 17. Component Value Selection for Si3215/Si3215M
Component Value Comments
R28
1/10 W, 1% resistor For VDD = 3.3 V: 26.1 k For VDD = 5.0 V: 37.4 k 1/10 W, 1% resistor For VCLAMP = 80 V: 541 k For VCLAMP = 85 V: 574 k For VCLAMP = 100 V: 676 k
R28 = (VDD + VBE)/148 A where VBE is the nominal VBE for Q9 R29 = VCLAMP/148 A where VCLAMP is the clamping voltage for VBAT
R29
Table 18. Component Value Selection Examples for Si3215M MOSFET/Transformer DC-DC Converter
VDC Maximum Ringing Load/Loop Resistance Transformer Ratio R18 R19, R20
3.3 V 5.0 V 12 V 24 V
3 REN/117 5 REN/117 5 REN/117 5 REN/117
1-2 1-2 1-3 1-4
0.06 0.10 0.6 2.1
7.15 k 16.5 k 56.2 k 121 k
Note: There are other system and software conditions that influence component value selection. Please refer to "AN45: Design Guide for the Si3210 DC-DC Converter" for detailed information.
Table 19. Component Value Selection Examples for Si3215 BJT/Inductor DC-DC Converter
VDC Maximum Ringing Load/Loop Resistance L1 R17 R18 R19, R20
5V 12 V 24 V
3 REN/117 5 REN/117 5 REN/117
67 H 150 H 220 H
150 162 175
0.15 0.56 2.0
16.5 k 56.2k 121 k
Note: There are other system and software conditions that influence component value selection, so please refer to "AN45: Design Guide for the Si3210 DC-DC Converter" for detailed information.
22
Rev. 0.92
Si3215
2. Functional Description
The ProSLIC(R) is a single, low-voltage CMOS device that provides all the SLIC, codec, and signal generation functions needed for a complete analog telephone interface. The ProSLIC performs all battery, overvoltage, ringing, supervision, codec, hybrid, and test (BORSCHT) functions. Unlike most monolithic SLICs, the Si3215 does not require externally-supplied high-voltage battery supplies. Instead, it generates all necessary battery voltages from a positive dc supply using its own dc-dc converter controller. Two fullyprogrammable tone generators can produce DTMF tones, phase-continuous FSK (caller ID) signaling, and call progress tones. The Si3201 linefeed interface IC performs all high-voltage functions. As an option, the Si3201 can also be replaced with low-cost discrete components as shown in the typical application circuit in Figure 12. The ProSLIC is ideal for short loop applications, such as terminal adapters, cable telephony, PBX/key systems, wireless local loop (WLL), and voice-over-IP solutions. The device meets all relevant LSSGR and CCITT standards. The linefeed provides programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission ringing voltage. Loop current and voltage are continuously monitored using an integrated A/D converter. Balanced 5 REN ringing with or without a programmable dc offset is integrated. The available offset, frequency, waveshape, and cadence options are designed to ring the widest variety of terminal devices and to reduce external controller requirements. A complete audio transmit and receive path is integrated, including ac impedance and hybrid gain. These features are software-programmable, allowing for a single hardware design to meet international requirements. Digital voice data transfer occurs over a standard PCM bus. Control data is transferred using a standard SPI. The device is available in 38-pin QFN or TSSOP packages.
2.1. Si3210 to Si3215 Differences
The Si3215 is very similar to the Si3210 in terms of its operation. The complete functionality of the Si3215 is covered in this data sheet. There are some hardware and software differences between the Si3215 and the Si3210 that are mentioned here for customers migrating designs from the Si3210 to the Si3215.
2.1.1. Hardware Changes
The Si3215 adds China and Japan impedances. See "2.7. Two-Wire Impedance Matching" on page 42. Pulse metering and DTMF detection are removed from the Si3215. The pinout on the QFN package has changed. See "5. Pin Descriptions: Si3215" on page 107. External resistors R8 and R9 are changed from 470 to 4.7 k. See the typical application circuit in Figure 12.
2.1.2. Software Changes
The sample rate for the two-tone oscillators has changed from 8 kHz to 16 kHz; therefore, the audio tone coefficient equation has changed. See "2.4.2. Oscillator Frequency and Amplitude" on page 33 for a complete description. The Si3215 is automatically calibrated for gain mismatch, and manual calibration is not required. Refer to "AN35: Si321x User's Quick Reference Guide". The Indirect Registers have been remapped. When porting code from the Si3210 to the Si3215, the indirect register access function needs to be modified. See "4. Indirect Registers" on page 101.
2.2. Linefeed Interface
The ProSLIC's linefeed interface offers a rich set of features and programmable flexibility to meet the broadest applications requirements. The dc linefeed characteristics are software-programmable; key current, voltage, and power measurements are acquired in real time and provided in software registers.
Rev. 0.92
23
Si3215
2.2.1. DC Feed Characteristics 2.2.2. Linefeed Architecture
The ProSLIC has programmable constant voltage and constant current zones as depicted in Figure 14. Open circuit TIP-to-RING voltage (VOC) defines the constant voltage zone and is programmable from 0 V to 94.5 V in 1.5 V steps. The loop current limit (ILIM) defines the constant current zone and is programmable from 20 mA to 41 mA in 3 mA steps. The ProSLIC has an inherent dc output resistance (RO) of 160 .
V (TIP-RING ) (V) Constant Voltage Zone
The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure 15 is a simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. The ProSLIC uses both voltage and current sensing to control TIP and RING. DC and AC line voltages on TIP and RING are measured through sense resistors RDC and RAC. The ProSLIC uses linefeed transistors QP and QN to drive TIP and RING. QDN isolates the high-voltage base of QN from the ProSLIC. The ProSLIC measures voltage at various nodes in order to monitor the linefeed current. RDC, RSE, and RBAT provide access to these measuring points. The sense circuitry is calibrated on-chip to guarantee measurement accuracy with standard external component tolerances. See "2.2.9. Linefeed Calibration" on page 29 for details.
2.2.3. Linefeed Operation States
VOC
R O =160 I LIM
Constant Current Zone I LO O P (m A)
Figure 14. Simplified DC Current/Voltage Linefeed Characteristic
The TIP-to-RING voltage (VOC) is offset from ground by a programmable voltage (VCM) to provide voltage headroom to the positive-most terminal (TIP in forward polarity states and RING in reverse polarity states) for carrying audio signals. Table 20 summarizes the parameters to be initialized before entering an active state.
The ProSLIC linefeed has eight states of operation as shown in Table 21. The state of operation is controlled using the Linefeed Control register (direct Register 64). The open state turns off all currents into the external bipolar transistors and can be used in the presence of fault conditions on the line and to generate Open Switch Intervals (OSIs). TIP and RING are effectively tri-stated with a dc output impedance of about 150 k. The ProSLIC can also automatically enter the open state if it detects excessive power being consumed in the external bipolar transistors. See "2.2.5. Power Monitoring and Line Fault Detection" on page 27 for more details. In the forward active and reverse active states, linefeed circuitry is on, and the audio signal paths are powered down. In the forward and reverse on-hook transmission states, audio signal paths are powered up to provide data transmission during an on-hook loop condition. The TIP Open state turns off all control currents to the external bipolar devices connected to TIP and provides an active linefeed on RING for ground start operation. The RING Open state provides similar operation with the RING drivers off and TIP active. The ringing state drives waveforms onto the line. programmable ringing
Table 20. Programmable Ranges of DC Linefeed Characteristics
Parameter ILIM VOC VCM Programmable Range 20 to 41 mA 0 to 94.5 V 0 to 94.5 V Default Value 20 mA 48 V 3V Register Bits ILIM[2:0] VOC[5:0] VCM[5:0] Location* Direct Register 71 Direct Register 72 Direct Register 73
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly.
24
Rev. 0.92
Si3215
2.2.4. Loop Voltage and Current Monitoring
The ProSLIC continuously monitors the TIP and RING voltages and external BJT currents. These values are available in registers 78-89. Table 22 lists the values that are measured and their associated registers. An internal A/D converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. The A/D updates the samples at an 800 Hz rate.
Two derived values are also reported: loop voltage and loop current. The loop voltage, VTIP - VRING, is reported as a 1-bit sign, 6-bit magnitude format. For ground start operation, the reported value is the RING voltage. The loop current, (IQ1 - IQ2 + IQ5 -IQ6)/2, is reported in a 1bit sign, 6-bit magnitude format. In RING open and TIP open states, the loop current is reported as (IQ1 - IQ2) + (IQ5 -IQ6).
Audio Codec A/D
Monitor A/D A/D
DSP
D/A D/A SLIC DAC
On-Chip
AC Control
AC Sense
DC Control
DC Sense
Battery Sense Emitter Sense
External Components
RAC CAC
AC Control Loop
Si3201
QP QDN
RBP
DC Control Loop
RDC
RSE
RBAT
TIP or RING
QN
RE VBAT
Figure 15. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown)
Rev. 0.92
25
Si3215
Table 21. ProSLIC Linefeed Operations
LF[2:0]* Linefeed State Description
000 001 010 011 100 101 110 111
Open Forward Active Forward On-Hook Transmission TIP Open Ringing Reverse Active Reverse On-Hook Transmission Ring Open
TIP and RING tri-stated. VTIP > VRING. VTIP > VRING; audio signal paths powered on. TIP tri-stated, RING active; used for ground start. Ringing waveform applied to TIP and RING. VRING > VTIP. VRING > VTIP; audio signal paths powered on. RING tri-stated, TIP active.
*Note: The Linefeed register (LF) is located in direct Register 64.
Table 22. Measured Real Time Linefeed Interface Characteristics
Parameter Measurement Range Resolution Register Bits Location*
Loop Voltage Sense (VTIP - VRING) Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 (VBAT) Battery Voltage Sense 2 (VBAT) Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense
-94.5 to +94.5 V -78.75 to +78.5 mA 0 to -95.88 V 0 to -95.88 V 0 to -95.88 V 0 to -95.88 V 0 to 81.35 mA 0 to 81.35 mA 0 to 9.59 mA 0 to 9.59 mA 0 to 80.58 mA 0 to 80.58 mA
1.5 V 1.25 mA 0.376 V 0.376 V 0.376 V 0.376 V 0.319 mA 0.319 mA 37.6 A 37.6 A 0.316 mA 0.316 mA
LVSP, LVS[6:0] LCSP, LCS[5:0] VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0]
Direct Register 78 Direct Register 79 Direct Register 80 Direct Register 81 Direct Register 82 Direct Register 83 Direct Register 84 Direct Register 85 Direct Register 86 Direct Register 87 Direct Register 88 Direct Register 89
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly.
26
Rev. 0.92
Si3215
2.2.5. Power Monitoring and Line Fault Detection
the type of fault condition present on the line. The value of each thermal low-pass filter pole is set according to the equation:
3 4096 thermal LPF register = ------------------ x 2 800 x
In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each external bipolar transistor. Real time output power of any one of the six linefeed transistors can be read by setting the power monitor pointer (direct Register 76) to point to the desired transistor and then reading the line power output monitor (direct Register 77). The real time power measurements are low-pass filtered and compared to a maximum power threshold. Maximum power thresholds and filter time constants are software-programmable and should be set for each transistor pair based on the characteristics of the transistors used. Table 23 describes the registers associated with this function. If the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. The ProSLIC sets the Power Alarm register bit, generates an interrupt (if enabled), and automatically enters the Open state (if AOPN = 1). This feature protects the external transistors from fault conditions and, combined with the loop voltage and current monitors, allows diagnosis of
where is the thermal time constant of the transistor package; 4096 is the full range of the 12-bit register, and 800 is the sample rate in Hertz. Generally, = 3 seconds for SOT223 packages and = 0.16 seconds for SOT23, but check with the manufacturer for the package thermal constant of a specific device. For example, the power alarm threshold and low-pass filter values for Q5 and Q6 using a SOT223 package transistor are computed as follows:
P MAX 7 7 1.28 PT56 = ------------------------------ x 2 = ----------------- x 2 = 5389 = 150D 0.0304 Resolution
Thus, indirect Register 21 should be set to 150Dh.
Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6.
Table 23. Associated Power Monitoring and Power Fault Registers
Parameter Description/ Range Resolution Register Bits Location*
Power Monitor Pointer Line Power Monitor Output
0 to 5 points to Q1 to Q6, respectively 0 to 7.8 W for Q1, Q2, Q5, Q6 0 to 0.9 W for Q3, Q4 0 to 7.8 W 0 to 0.9 W 0 to 7.8 W
N/A 30.4 mW 3.62 mW
PWRMP[2:0] PWROM[7:0]
Direct Register 76 Direct Register 77
Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 & Q2 Thermal LPF Pole, Q3 & Q4 Thermal LPF Pole, Q5 & Q6 Power Alarm Interrupt Pending
30.4 mW 3.62 mW 30.4 mW
PPT12[7:0] PPT34[7:0] PPT56[7:0] NQ12[7:0] NQ34[7:0] NQ56[7:0] QnAP[n+1], where n = 1 to 6
Indirect Register 19 Indirect Register 20 Indirect Register 21 Indirect Register 24 Indirect Register 25 Indirect Register 26 Direct Register 19
See equation above. See equation above. See equation above. Bits 2 to 7 correspond to Q1 to Q6, respectively N/A
Rev. 0.92
27
Si3215
Table 23. Associated Power Monitoring and Power Fault Registers (Continued)
Power Alarm Interrupt Enable Bits 2 to 7 correspond to Q1 to Q6, respectively 0 = manual mode 1 = enter open state upon power alarm N/A QnAE[n+1], where n = 1 to 6 AOPN Direct Register 22
Power Alarm Automatic/Manual Detect
N/A
Direct Register 67
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28 through 31).
LCS LVS Input Signal Processor ISP_OUT Digital LPF + Debounce Filter - NCLR LFS LCVE HYSTEN Loop Closure Threshold LCDI LCIE LCR LCIP
Interrupt Logic
LCRT LCRTL
Figure 16. Loop Closure Detection 2.2.6. Loop Closure Detection
A loop closure event signals that the terminal equipment has gone off-hook during on-hook transmission or onhook active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter. The functional blocks required to implement loop closure detection are shown in Figure 16. The primary input to the system is the Loop Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input Signal Processor when the ProSLIC is in the on-hook transmission or on-hook active linefeed state, as indicated by the Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a programmable digital low-pass filter, which removes unwanted ac signal components before threshold detection. The output of the low-pass filter is compared to a programmable threshold, LCRT (indirect register 15). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval,
LCDI (direct Register 69). If the debounce interval has been satisfied, the LCR bit will be set to indicate that a valid loop closure has occurred. A loop closure interrupt is generated if enabled by the LCIE bit (direct Register 22). Table 24 lists the registers that must be written or monitored to correctly detect a loop closure condition.
2.2.7. Loop Closure Threshold Hysteresis
Programmable hysteresis to the loop closure threshold can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect Register 15) and LCRTL (indirect Register 66), which set the upper and lower bounds, respectively.
2.2.8. Voltage-Based Loop Closure Detection
An optional voltage-based loop closure detection mode can be enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode, the loop voltage is compared to the loop closure threshold register (LCRT), which represents a minimum voltage threshold instead of a maximum current threshold. If hysteresis is also enabled, LCRT represents the upper voltage boundary, and LCRTL represents the lower voltage boundary for hysteresis. Although voltage-based loop closure
28
Rev. 0.92
Si3215
detection is an option, the default current-based loop closure detection is recommended.
2.3. Battery Voltage Generation and Switching
The Si3215 integrates a dc-dc converter controller that dynamically regulates a single output voltage. This mode eliminates the need to supply large external battery voltages. Instead, it converts a single positive input voltage into the real-time battery voltage needed for any given state according to programmed linefeed parameters.
Table 24. Register Set for Loop Closure Detection
Parameter Register Location Loop Closure LCIP Direct Reg. 19 Interrupt Pending Loop Closure LCIE Direct Reg. 22 For single to low channel count applications, the Si3215 Interrupt Enable Loop Closure Threshold LCRT[5:0] Indirect Reg. 15 proves to be an economical choice, as the dc-dc Loop Closure LCRTL[5:0] Indirect Reg. 66 converter eliminates the need to design and build highvoltage power supplies. Threshold--Lower Loop Closure Filter NCLR[12:0] Indirect Reg. 22 2.3.1. DC-DC Converter General Description Coefficient The dc-dc converter dynamically generates the large Loop Closure Detect LCR Direct Reg. 68 negative voltages required to operate the linefeed interface. The Si3215 acts as the controller for a buckStatus (monitor only) Loop Closure Detect LCDI[6:0] Direct Reg. 69 boost dc-dc converter that converts a positive dc voltage into the desired negative battery voltage. In Debounce Interval Hysteresis Enable HYSTEN Direct Reg. 108 addition to eliminating external power supplies, this allows the Si3215 to dynamically control the battery Voltage-Based Loop LCVE Direct Reg. 108 voltage to the minimum required for any given mode of Closure operation. 2.2.9. Linefeed Calibration
An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset. It is recommended that a calibration be executed following system power-up. Upon release of the chip reset, the Si3215 will be in the open state. After powering up the dc-dc converter and allowing it to settle for time (tsettle) the calibration can be initiated. Additional calibrations may be performed, but only one calibration should be necessary as long as the system remains powered up. During calibration, VBAT, VTIP, and VRING voltages are controlled by the calibration engine to provide the correct external voltage conditions for the algorithm. Calibration should be performed in the on-hook state. RING or TIP must not be connected to ground during the calibration. When using the Si3201, automatic calibration routines for RING gain mismatch and TIP gain mismatch should not be performed. Instead of running these two calibrations automatically, consult "AN35: Si321x User's Quick Reference Guide", and follow the instructions for manual calibration.
Two different dc-dc circuit options are offered: a BJT/ inductor version and a MOSFET/transformer version. Due to the differences on the driving circuits, there are two different versions of the Si3215. The Si3215 supports the BJT/inductor circuit option, and the Si3215M version supports the MOSFET solution. The only difference between the two versions is the polarity of the DCFF pin with respect to the DCDRV pin. For the Si3215, DCDRV and DCFF are of opposite polarity. For the Si3215M, DCDRV and DCFF are of the same polarity. Table 25 summarizes these differences.
Table 25. Si3215 and Si3215M Differences
Device DCFF Signal Polarity DCPOL
Si3215 Si3215M
= DCDRV = DCDRV
0 1
Notes: 1. DCFF signal polarity with respect to DCDRV signal. 2. Direct Register 93, bit 5; This is a read-only bit.
Extensive design guidance on each of these circuits can be obtained from "AN45: Design Guide for the Si3210 DC-DC Converter" and from an interactive dc-dc converter design spreadsheet. Both of these documents are available on the Silicon Laboratories website (www.silabs.com).
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2.3.2. BJT/Inductor Circuit Option Using Si3215
The BJT/Inductor circuit option, as defined in Figure 10 on page 17, offers a flexible, low-cost solution. Depending on selected L1 inductance value and the switching frequency, the input voltage (VDC) can range from 5 V to 30 V. By nature of a dc-dc converter's operation, peak and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply. For this solution, a PNP power BJT (Q7) switches the current flow through low ESR inductor L1. The Si3215 uses the DCDRV and DCFF pins to switch Q7 on and off. DCDRV controls Q7 through NPN BJT Q8. DCFF is ac coupled to Q7 through capacitor C10 to assist R16 in turning off Q7. Therefore, DCFF must have opposite polarity to DCDRV, and the Si3215 (not Si3215M) must be used.
2.3.3. MOSFET/Transformer Circuit Option Using Si3215M
regulator circuit within the Si3215 is a highperformance, pulse-width modulation controller. The control pins are driven by the PWM controller logic in the Si3215. The regulated output voltage (VBAT) is sensed by the SVBAT pin and used to detect whether the output voltage is above or below an internal reference for the desired battery voltage. The dc monitor pins, SDCH and SDCL, monitor input current and voltage to the dc-dc converter external circuitry. If an overload condition is detected, the PWM controller will turn off the switching transistor for the remainder of a PWM period to prevent damage to external components. It is important that the proper value of R18 be selected to ensure safe operation. Guidance is given in AN45. The PWM controller operates at a frequency set by the dc-dc Converter PWM register (direct Register 92). During a PWM period, the outputs of the control pins, DCDRV and DCFF, are asserted for a time given by the read-only PWM Pulse Width register (direct Register 94). The dc-dc converter must be off for some time in each cycle to allow the inductor or transformer to transfer its stored energy to the output capacitor, C9. This minimum off time can be set through the dc-dc Converter Switching Delay register, (direct Register 93). The number of 16.384 MHz clock cycles that the controller is off is equal to DCTOF (bits 0 through 4) plus 4. If the dc Monitor pins detect an overload condition, the dc-dc converter interrupts its conversion cycles regardless of the register settings to prevent component damage. These inputs should be calibrated by writing the DCCAL bit (bit 7) of the dc-dc Converter Switching Delay register, direct Register 93, after the dc-dc converter has been turned on. Because the Si3215 dynamically regulates its own battery supply voltage using the dc-dc converter controller, the battery voltage (VBAT) is offset from the negative-most terminal by a programmable voltage (VOV) to allow voltage headroom for carrying audio signals. As mentioned previously, the Si3215 dynamically adjusts VBAT to suit the particular circuit requirement. To illustrate this, the behavior of VBAT in the active state is shown in Figure 17. In the active state, the TIP-to-RING open circuit voltage is kept at VOC in the constant voltage region while the regulator output voltage, VBAT = VCM + VOC + VOV. When the loop current attempts to exceed ILIM, the dc line driver circuit enters constant current mode allowing the TIP to RING voltage to track RLOOP. As the TIP terminal is kept at a constant voltage, it is the RING
The MOSFET/transformer circuit option, as defined in Figure 11, offers higher power efficiencies across a larger input voltage range. Depending on the transformers primary inductor value and the switching frequency, the input voltage (VDC) can range from 3.3 V to 35 V. Therefore, it is possible to power the entire ProSLIC solution from a single 3.3 V or 5 V power supply. By nature of a dc-dc converter's operation, peak and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply (number of REN supported). For this solution, an n-channel power MOSFET (M1) switches the current flow through a power transformer T1. T1 is specified in "AN45: Design Guide for the Si3210 DC-DC Converter" and includes several taps on the primary side to facilitate a wide range of input voltages. The Si3215M must be used for the application circuit depicted in Figure 11 on page 19 because the DCFF pin is used to drive M1 directly and, therefore, must be the same polarity as DCDRV. DCDRV is not used in this circuit option; connecting DCFF and DCDRV together is not recommended.
2.3.4. DC-DC Converter Architecture
The control logic for a pulse width modulated (PWM) dcdc converter is incorporated in the Si3215. Output pins, DCDRV and DCFF, are used to switch a bipolar transistor or MOSFET. The polarity of DCFF is opposite that of DCDRV. The dc-dc converter circuit is powered on when the DCOF bit in the Powerdown Register (direct Register 14, bit 4) is cleared to 0. The switching
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terminal voltage that tracks RLOOP, and, as a result, the |VBAT| voltage will also track RLOOP. In this state, |VBAT| = ILIM x RLOOP + VCM +VOV. As RLOOP decreases below the VOC/ILIM mark, the regulator output voltage can continue to track RLOOP (TRACK = 1), or the RLOOP tracking mechanism is stopped when |VBAT| = |VBATL| (TRACK = 0). The former case is the more common application and provides the maximum power dissipation savings. In principle, the regulator output voltage can go as low as |VBAT| = VCM+ VOV, offering significant power savings. When TRACK = 0, |VBAT| will not decrease below VBATL. The RING terminal voltage, however, continues to decrease with decreasing RLOOP. The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment, which, in order to initiate certain data transmission modes, goes briefly on-hook to measure the line voltage to determine whether there is any other off-hook terminal equipment on the same line. TRACK = 0 mode is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds) and cannot change rapidly for TRACK = 1 mode. Therefore, the brief on-hook voltage measurement would yield approximately the same voltage as the off-hook line voltage and cause the terminal equipment to incorrectly sense another offhook terminal.
VOC
Constant I Region
ILIM VCM
Constant V Region
RLOOP VTIP
TR A
VBATL
CK =1
|VTIP - VRING|
VOV
VOC
TRACK=0
VOV
VRING VBAT
V
Figure 17. VTIP, VRING, and VBAT in the Forward Active State
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Table 26. Associated Relevant DC-DC Converter Registers
Parameter Range Resolution Register Bit Location
DC-DC Converter Power-Off Control DC-DC Converter Calibration Enable/Status DC-DC Converter PWM Period DC-DC Converter Min. Off Time High Battery Voltage--VBATH Low Battery Voltage--VBATL VOV
N/A N/A 0 to 15.564 s (0 to 1.892 s) + 4 ns 0 to -94.5 V 0 to -94.5 V 0 to -9 V or 0 to -13.5 V
N/A N/A 61.035 ns 61.035 ns 1.5 V 1.5 V 1.5 V
DCOF DCCAL DCN[7:0] DCTOF[4:0] VBATH[5:0] VBATL[5:0] VMIND[3:0] VOV
Direct Register 14 Direct Register 93 Direct Register 92 Direct Register 93 Direct Register 74 Direct Register 75 Indirect Register 64 Direct Register 66
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
2.3.5. DC-DC Converter Enhancements
2.4. Tone Generation
Two digital tone generators are provided in the ProSLIC. They allow the generation of a wide variety of single- or dual-tone frequency and amplitude combinations and spare the user the effort of generating the required POTS signaling tones on the PCM highway. DTMF, FSK (caller ID), call progress, and other tones can all be generated on-chip. The tones can be sent to either the receive or transmit paths (see Figure 22 on page 40).
2.4.1. Tone Generator Architecture
The Si3215 supports two enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5). The second enhancement is an audio band filter that removes audio band noise from the dc-dc converter control loop. This option is enabled by setting DCFIL = 1 (direct Register 108, bit 1).
2.3.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the dc-dc converter during a ringing burst is set using the VBATH register (direct Register 74). VBATH can be set between 0 and -94.5 V in 1.5 V steps. To avoid clipping the ringing signal, VBATH must be set larger than the ringing amplitude. At the end of each ringing burst, the dc-dc converter adjusts back to active state regulation as described above.
A simplified diagram of the tone generator architecture is shown in Figure 18. The oscillator, active/inactive timers, interrupt block, and signal routing block are connected to give the user flexibility in creating audio signals. Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. These registers are described in more detail in Table 27.
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8 kHz Clock OnE OZn 16 kHz Clock
Zero Cross OSSn
Enable
16-Bit Modulo Counter
OAT Expire OIT Expire
Zero Cross Logic
Load Logic
Two-Pole Resonance Register Oscillator
Load
to TX Path
Signal Routing
to RX Path
OATn OATnE OITn OITnE INT Logic INT Logic OnIP REL*
OSCn OnSO OnIE OnAP OSCnY OSCnX
OnAE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively
Figure 18. Simplified Tone Generator Diagram 2.4.2. Oscillator Frequency and Amplitude
Each of the two-tone generators contains a two-pole resonate oscillator circuit with a programmable frequency and amplitude, which are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two oscillators is 16 kHz. The equations are as follows: coeffn = cos(2 fn/16 kHz), where fn is the frequency to be generated; OSCn = coeffn x (215);
Desired V rms 15 1 1 - coeff OSCnX = -- x ----------------------- x ( 2 - 1 ) x -----------------------------------4 1.11 V rms 1 + coeff
21336 coeff 2 = cos ------------------- = 0.86550 16000
OSC2 = 0.86550 (215) = 28361 = 6EC8h
1 15 OSC2X = -- x 0.13450 x ( 2 - 1 ) x 0.5 = 1098 = 44Bh -------------------4 1.86550
OSC2Y = 0 The computed values above would be written to the corresponding registers to initialize the oscillators. Once the oscillators are initialized, the oscillator control registers can be accessed to enable the oscillators and direct their outputs.
2.4.3. Tone Generator Cadence Programming
where desired Vrms is the amplitude to be generated; OSCnY = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. For example, in order to generate a DTMF digit of 8, the two required tones are 852 Hz and 1336 Hz. Assuming the generation of half-scale values (ignoring twist) is desired, the following values are calculated:
2852 coeff 1 = cos ---------------- = 0.94455 16000 OSC1 = 0.94455 ( 2 ) = 30951 = 78E6h 1 15 OSC1X = -- x 0.05545 x ( 2 - 1 ) x 0.5 = 692 = 2B3h -------------------4 1.94455
15
Each of the two tone generators contains two timers, one for setting the active period and one for setting the inactive period. The oscillator signal is generated during the active period and suspended during the inactive period. Both the active and inactive periods can be programmed from 0 to 8 seconds in 125 s steps. The active period time interval is set using OAT1 (direct registers 36 and 37) for tone generator 1 and OAT2 (direct registers 40 and 41) for tone generator 2. To enable automatic cadence for tone generator 1, define the OAT1 and OIT1 registers and then set the O1TAE bit (direct Register 32, bit 4) and O1TIE bit (direct Register 32, bit 3). This enables each of the timers to control the state of the Oscillator Enable bit, O1E (direct Register 32, bit 2). The 16-bit counter will begin counting until the active timer expires, at which time the 16-bit counter will reset to zero and begin
OSC1Y = 0
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counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures that each oscillator pulse ends without a dc component. The timing diagram in Figure 19 is an example of an output cadence using the zero crossing feature. One-shot oscillation can be achieved by enabling O1E and O1TAE. Direct control over the cadence can be achieved by controlling the O1E bit (direct Register 32, bit 2) directly if O1TAE and O1TIE are disabled. The operation of tone generator 2 is identical to that of tone generator 1 using its respective control registers.
Note: Tone Generator 2 should not be enabled simultaneously with the ringing oscillator due to resource sharing within the hardware.
Continuous-phase frequency-shift keying (FSK) waveforms may be created using tone generator 1 (not available on tone generator 2) by setting the REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer (OAT1).
Table 27. Associated Tone Generator Registers
Tone Generator 1 Parameter Description / Range Register Bits Location
Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control
Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 seconds 0 to 8 seconds Status and control registers
Tone Generator 2
OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OAT1[15:0] OIT1[15:0] OSS1, REL, OZ1, O1TAE, O1TIE, O1E, O1SO[1:0]
Register
Indirect Register 0 Indirect Register 1 Indirect Register 2 Direct Registers 36 & 37 Direct Register 38 & 39 Direct Register 32
Parameter
Description/Range
Location
Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 initial phase coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer Oscillator 2 Control
Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 seconds 0 to 8 seconds Status and control registers
OSC2[15:0] OSC2X[15:0] OSC2Y[15:0] OAT2[15:0] OIT2[15:0] OSS2, OZ2, O2TAE, O2TIE, O2E, O2SO[1:0]
Indirect Register 3 Indirect Register 4 Indirect Register 5 Direct Registers 40 & 41 Direct Register 42 & 43 Direct Register 33
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O1E
0,1
...
..., O AT1 0,1 ...
..., OIT1 0,1 ...
..., O AT1 0,1 ...
... ...
OSS1
Tone Gen. 1 Signal Output
Figure 19. Tone Generator Timing Diagram 2.4.4. Enhanced FSK Waveform Generation
2.5. Ringing Generation
The ProSLIC provides fully-programmable internal balanced ringing with or without a dc offset to ring a wide variety of terminal devices. All parameters associated with ringing, including ringing frequency, waveform, amplitude, dc offset, and ringing cadence, are software-programmable. Both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable. Ringing signals of up to 88 V peak or more can be generated, enabling the ProSLIC to drive a 5 REN (1380 + 40 F) ringer load across loop lengths of 2000 feet (160 ) or more.
2.5.1. Ringing Architecture
Enhanced FSK generation capabilities can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect registers 69-74. The user need only indicate 0-to-1 and 1-to-0 transitions in the information stream. By writing to FSKDAT (direct Register 52), this mode applies a 24 kHz sample rate to tone generator 1 to give additional resolution to timers and frequency generation. "AN32: Si321x Frequency Shift Keying (FSK) Modulation" gives detailed instructions on how to implement FSK in this mode. Additionally, sample source code is available from Silicon Laboratories upon request.
2.4.5. Tone Generator Interrupts
Both the active and inactive timers can generate their own interrupt to signal "on/off" transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the O1AE and O1IE bits (direct Register 21, bits 0 and 1, respectively). Timer interrupts for tone generator 2 are O2AE and O2IE (direct Register 21, bits 2 and 3, respectively). A pending interrupt for each of the timers is determined by reading the O1AP, O1IP, O2AP, and O2IP bits in the Interrupt Status 1 register (direct Register 18, bits 0 through 3, respectively).
The ringing generator architecture is nearly identical to that of the tone generator. The sinusoid ringing waveform is generated using an internal two-pole resonance oscillator circuit with programmable frequency and amplitude. However, since ringing frequencies are very low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 kHz rate instead of 8 kHz. The ringing generator has two timers that function the same as for the tone generator timers. They allow on/off cadence settings up to 8 seconds on/ 8 seconds off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. Table 28 summarizes the list of registers used for ringing generation.
Note: Tone generator 2 should not be enabled concurrently with the ringing generator due to resource sharing within the hardware.
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Table 28. Registers for Ringing Generation
Parameter Range/ Description Register Bits TSWS RVO Location
Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage Ringing dc voltage offset Ringing frequency Ringing amplitude Ringing initial phase
Common Mode Bias Adjust During Ringing
Sine/Trapezoid Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled 0 to 8 seconds 0 to 8 seconds Ringing State = 100b 0 to -94.5 V 0 to 94.5 V 15 to 100 Hz 0 to 94.5 V Sets initial phase for sinewave and period for trapezoid 0 to 22.5 V
Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Registers 48 and 49 Direct Registers 50 and 51 Direct Register 64 Direct Register 74 Indirect Register 6 Indirect Register 7 Indirect Register 8 Indirect Register 9
RTAE RTIE ROE RAT[15:0] RIT[15:0] LF[2:0] VBATH[5:0] ROFF[15:0] RCO[15:0] RNGX[15:0] RNGY[15:0]
VCMR[3:0]
Indirect Register 27
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28 through 31).
When the ringing state is invoked by writing LF[2:0] = 100 (direct Register 64), the ProSLIC will go into the ringing state and start the first ring. At the expiration of RAT, the ProSLIC will turn off the ringing waveform and go to the on-hook transmission state. At the expiration of RIT, ringing will again be initiated. This process will continue as long as the two timers are enabled and the Linefeed Control register is set to the ringing state.
2.5.2. Sinusoidal Ringing
In selecting a ringing amplitude, the peak TIP-to-RING ringing voltage must be greater than the selected onhook line voltage setting (VOC, direct Register 72). For example, to generate a 70 VPK, 20 Hz ringing signal, the equations are as follows:
2 x 20coeff = cos ---------------------- = 0.99211 1000 Hz RCO = 0.99211 x ( 2 ) = 32509 = 7EFDh
15 70 1 RNGX = -- x 0.00789 x 2 x ----- = 376 = 0177h -------------------96 4 1.99211 15
1 15 Desired V PK ( 0 to 94.5 V ) 1 - coeff RNGX = -- x ----------------------- x 2 x ----------------------------------------------------------------------4 96 V 1 + coeff RNGY = 0
To configure the ProSLIC for sinusoidal ringing, the frequency and amplitude are initialized by writing to the following indirect registers: RCO, RNGX, and RNGY. The equations for RCO, RNGX, and RNGY are as follows:
RCO = coeff x ( 2 )
15
RNGY = 0
where
2f coeff = cos ---------------------- 1000 Hz
and f = desired ringing frequency in hertz.
In addition, the user must select the sinusoidal ringing waveform by writing TSWS = 0 (direct Register 34, bit 0).
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2.5.3. Trapezoidal Ringing
(20 Hz), the rise time requirement is 0.0153 seconds.
RCO ( 20 Hz, 1.3 crest factor ) 2 x 24235 = ------------------------------------- = 396 = 018Ch 0.0153 x 8000
In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal ringing. Figure 20 illustrates a trapezoidal ringing waveform with offset VROFF.
VTIP-RING
In addition, the user must select the trapezoidal ringing waveform by writing TSWS = 1 in direct Register 34.
2.5.4. Ringing DC voltage Offset
VROFF T=1/freq tRISE time
A dc offset can be added to the ac ringing waveform by defining the offset voltage in ROFF (indirect Register 6). The offset, VROFF, is added to the ringing signal when RVO is set to 1 (direct Register 34, bit 1). The value of ROFF is calculated as follows:
V ROFF 15 ROFF = ----------------- x 2 96
2.5.5. Linefeed Considerations During Ringing
Figure 20. Trapezoidal Ringing Waveform
To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations:
1 RNGY = -- x Period x 8000 2 Desired V PK 15 RNGX = ----------------------------------- x ( 2 ) 96 V 2 x RNGX RCO = -------------------------------t RISE x 8000
Care must be taken to keep the generated ringing signal within the ringing voltage rails (GNDA and VBAT) to maintain proper biasing of the external bipolar transistors. If the ringing signal nears the rails, a distorted ringing signal and excessive power dissipation in the external transistors will result. To prevent this invalid operation, set the VBATH value (direct Register 74) to a value higher than the maximum peak ringing voltage. The following discussion outlines the considerations and equations that govern the selection of the VBATH setting for a particular desired peak ringing voltage. First, the required amount of ringing overhead voltage, VOVR, is calculated based on the maximum value of current through the load, ILOAD,PK, the minimum current gain of Q5 and Q6, and a reasonable voltage required to keep Q5 and Q6 out of saturation. For ringing signals up to VPK = 87 V, VOVR = 7.5 V is a safe value. However, to determine VOVR for a specific case, use the following equations.
V AC,PK N REN I LOAD,PK = ------------------ + I OS = V AC,PK x ----------------- + I OS R LOAD 6.9 k
RCO is a value that is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform.
3 1t RISE = -- T 1 - ---------- 2 4 CF
where: NREN is the ringing REN load (max value = 5), IOS is the offset current flowing in the line driver circuit (max value = 2 mA), and VAC,PK = amplitude of the ac ringing waveform. It is good practice to provide a buffer of a few more milliamperes for ILOAD,PK to account for possible line leakages, etc. The total ILOAD,PK current should be smaller than 80 mA.
where T = ringing period, and CF = desired crest factor. For example, to generate a 71 VPK, 20 Hz ringing signal, the equations are as follows:
1 1RNGY ( 20 Hz ) = -- x --------------- x 8000 = 200 = C8h 2 20 Hz
15 71 RNGX ( 71 V PK ) = ----- x 2 = 24235 = 5EABh 96
For a crest factor of 1.3 and a period of 0.05 seconds
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+1 V OVR = I LOAD,PK x ------------ x ( 80.6 + 1 V )
2.5.6. Ring Trip Detection
where is the minimum expected current gain of transistors Q5 and Q6. The minimum value for VBATH is, therefore, given by the following:
VBATH = V AC,PK + V ROFF + V OVR
The ProSLIC is designed to create a fully balanced ringing waveform, meaning that the TIP and RING common mode voltage, (VTIP + VRING)/2, is fixed. This voltage is referred to as VCM_RING and is automatically set to the following:
VBATH - VCMR VCM_RING = --------------------------------------------2
A ring trip event signals that the terminal equipment has gone off-hook during the ringing state. The ProSLIC performs ring trip detection digitally using its on-chip A/D converter. The functional blocks required to implement ring trip detection are shown in Figure 21. The primary input to the system is the loop current sense (LCS) value provided by the current monitoring circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the ringing state as indicated by the Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low-pass filter, which removes unwanted ac signal components before threshold detection. The output of the low-pass filter is compared to a programmable threshold, RPTP (indirect Register 16). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the ring trip debounce interval, RTDI[6:0] (direct Register 70). If the debounce interval has been satisfied, the RTP bit of direct Register 68 will be set to indicate that a valid ring trip has occurred. A ring trip interrupt is generated if enabled by the RTIE bit (direct Register 22). Table 29 lists the registers that must be written or monitored to correctly detect a ring trip condition. The recommended values for RPTP, NRTP, and RTDI vary according to the programmed ringing frequency. Register values for various ringing frequencies are given in Table 30.
VCMR is an indirect register that provides the headroom by the ringing waveform with respect to the VBATH rail. The value is set as a 4-bit setting in indirect Register 27 with an LSB voltage of 1.5 V/LSB. Register 27 should be set with the calculated VOVR to provide voltage headroom during ringing. The ProSLIC has a mode to briefly increase the maximum differential current limit between the voltage transition of TIP and RING from ringing to a dc linefeed state. This mode is enabled by setting ILIMEN = 1 (direct Register 108, bit 7).
LCS
Input Signal Processor
ISP_OUT
Digital LPF
+
DBIRAW
Debounce Filter
RTP
Interrupt Logic
RTIP
- NRTP LFS Ring Trip Threshold RTDI RTIE
RPTP
Figure 21. Ring Trip Detector
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Table 29. Associated Registers for Ring Trip Detection
Parameter Register Location
Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only)
RTIP RTIE RTDI[6:0] RPTP[5:0] NRTP[12:0] RTP
Direct Register 19 Direct Register 22 Direct Register 70 Indirect Register 16 Indirect Register 23 Direct Register 68
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
Table 30. Recommended Ring Trip Values for Ringing
Ringing Frequency NRTP RPTP RTDI
Hz 16.667 20 30 40 50 60
decimal 64 100 112 128 213 256
hex 0200 0320 0380 0400 06A8 0800
decimal 34 mA 34 mA 34 mA 34 mA 34 mA 34 mA
hex 3600 3600 3600 3600 3600 3600
decimal 15.4 ms 12.3 ms 8.96 ms 7.5 ms 5 ms 4.8 ms
hex 0F 0B 09 07 05 05
2.6. Audio Path
Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loop-back modes. The signal path block diagram is shown in Figure 22.
2.6.1. Transmit Path
In the transmit path, the analog signal fed by the external ac coupling capacitors is amplified by the analog transmit amplifier, ATX, prior to the A/D converter. The gain of the ATX is user-selectable to one of mute/-3.5/0/3.5 dB options. The main role of ATX is to coarsely adjust the signal swing to be as close as possible to the full-scale input of the A/D converter in order to maximize the signal-to-noise ratio of the transmit path. After passing through an anti-aliasing filter, the analog signal is processed by the A/D converter, producing an 8 kHz, 16-bit wide, linear PCM
data stream. The standard requirements for transmit path attenuation for signals above 3.4 kHz are implemented as part of the combined decimation filter characteristic of the A/D converter. One more digital filter is available in the transmit path, THPF. THPF implements the high-pass attenuation requirements for signals below 65 Hz. The linear PCM data stream output from THPF is amplified by the transmit-path programmable gain amplifier, ADCG, which can be programmed from - dB to 6 dB. The final step in the transmit path signal processing is the user-selectable A-law or -law compression, which can reduce the data stream word width to 8 bits. Depending on the PCM_Mode register selection, every 8-bit compressed serial data word will occupy one time slot on the PCM highway, or every 16-bit uncompressed serial data word will occupy two time slots on the PCM highway.
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40
Transmit Path HYBP From Billing Tone DAC H
Off Chip
On Chip
ATX
Digital TX
Si3215
+-
A/D
Decimation Filter
THPF
ADCG
Mute
+
Full Analog Loopback
/A-law Compressor Serial Output
Analog Loopback
Digital Loopback
TXM
H
ALM1 DLM
Dual Tone Generator
ALM2
HYBA
TIP RING
XAC D/A
-
ARX
Interpolation Filter
Digital RX /A-law Expander Serial Input
+
RHPF DACG From Billing Tone DAC
+
Mute
Ibuf
Gm
RAC RXM
Rev. 0.92
Figure 22. AC Signal Path Block Diagram
Si3215
2.6.2. Receive Path
In the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16bit word. DACG is the receive path programmable gain amplifier, which can be programmed from - dB to 6 dB. An 8 kHz, 16-bit signal is then provided to a D/A converter. The resulting analog signal is amplified by the analog receive amplifier, ARX, which is userselectable to one of mute/-3.5/0/3.5 dB options. It is then applied at the input of the transconductance amplifier (Gm), which drives the off-chip current buffer (IBUF).
2.6.3. Audio Characteristics
frequencies greater than 4 kHz, the plot in Figure 4 should be interpreted as the maximum allowable magnitude of any spurious signals that are generated when a PCM data stream representing a sine wave signal in the range of 300 Hz to 3.4 kHz at a level of 0 dBm0 is applied at the digital input. The group delay distortion in either path is limited to no more than the levels indicated in Figure 5 on page 10. The reference in Figure 5 on page 10 is the smallest group delay for a sine wave in the range of 500 Hz to 2500 Hz at 0 dBm0. The block diagram for the voice-band signal processing paths are shown in Figure 22. Both the receive and the transmit paths employ the optimal combination of analog and digital signal processing to provide the maximum performance while, at the same time, offering sufficient flexibility to allow users to optimize for their particular application of the ProSLIC. All programmable signal-processing blocks are symbolically indicated in Figure 22 by a dashed arrow across them. The two-wire (TIP/RING) voice-band interface to the ProSLIC is implemented using a small number of external components. The receive path interface consists of a unity-gain current buffer, IBUF, while the transmit path interface is simply an ac coupling capacitor. Signal paths, although implemented differentially, are shown as single-ended for simplicity.
2.6.4. Transhybrid Balance
The dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced by the -law or the A-law compression process. Figure 1 on page 7 specifies the minimum signal-to-noise-and-distortion ratio for either path for a sine wave input of 200 Hz to 3400 Hz. Both the -law and the A-law speech encoding allow the audio codec to transfer and process audio signals larger than 0 dBm0 without clipping. The maximum PCM code is generated for a -law encoded sine wave of 3.17 dBm0 or an A-law encoded sine wave of 3.14 dBm0. The ProSLIC overload clipping limits are driven by the PCM encoding process. Figure 2 on page 7 shows the acceptable limits for the analog-to-analog fundamental power transfer-function, which bounds the behavior of ProSLIC. The transmit path gain distortion versus frequency is shown in Figure 3 on page 8. The same figure also presents the minimum required attenuation for any outof-band analog signal that may be applied on the line. Note the presence of a high-pass filter transfer-function, which ensures at least 30 dB of attenuation for signals below 65 Hz. The low-pass filter transfer function that attenuates signals above 3.4 kHz has to exceed the requirements specified by the equations in Figure 3 on page 8, and it is implemented as part of the A-to-D converter. The receive path transfer function requirement, shown in Figure 4 on page 9, is very similar to the transmit path transfer function. The most notable difference is the absence of the high-pass filter portion. The only other differences are the maximum 2 dB attenuation at 200 Hz (as opposed to 3 dB for the transmit path) and the 28 dB of attenuation for any frequency above 4.6 kHz. The PCM data rate is 8 kHz and, thus, no frequencies greater than 4 kHz can be digitally encoded in the data stream. From this point of view, at
The ProSLIC provides programmable transhybrid balance with gain block H. (See Figure 22.) In the ideal case where the synthesized SLIC impedance matches exactly the subscriber loop impedance, the transhybrid balance should be set to subtract a -6 dB level from the transmit path signal. The transhybrid balance gain can be adjusted from -2.77 dB to +4.08 dB around the ideal setting of -6 dB by programming the HYBA[2:0] bits of the Hybrid Control register (direct Register 11). Note that adjusting any of the analog or digital gain blocks will not require any modification of the transhybrid balance gain block, as the transhybrid gain is subtracted from the transmit path signal prior to any gain adjustment stages. The transhybrid balance can also be disabled, if desired, using the appropriate register setting.
2.6.5. Loopback Testing
Four loopback test options are available in the ProSLIC: The full analog loopback (ALM2) tests almost all the circuitry of both the transmit and receive paths. The compressed 8-bit word transmit data stream is fed back serially to the input of the receive path expander. (See Figure 22.) The signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output of
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the receive path. An additional analog loopback (ALM1) takes the digital stream at the output of the A/D converter and feeds it back to the D/A converter. (See Figure 22.) The signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output of the receive path. This loopback option allows the testing of the analog signal processing circuitry of the Si3215 completely independently of any activity in the DSP. The full digital loopback tests almost all the circuitry of both the transmit and receive paths. The analog signal at the output of the receive path is fed back to the input of the transmit path by way of the hybrid filter path. (See Figure 22.) The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can bypass the companding process and interface directly to the 16-bit data. An additional digital loopback (DLM) takes the digital stream at the input of the D/A converter in the receive path and feeds it back to the transmit A/D digital filter. The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. This loopback option allows the testing of the digital signal processing circuitry of the Si3215 completely independently of any analog signal processing activity. The user can bypass the companding process and interface directly to the 16-bit data. The ProSLIC also provides a means of compensating for degraded subscriber loop conditions involving excessive line capacitance (leakage). The CLC[1:0] bits of direct Register 10 increase the ac signal magnitude to compensate for the additional loss at the high end of the audio frequency range. The default setting of CLC[2:0] assumes no line capacitance. The Si3215 supports the option to remove the internal reference resistor used to synthesize ac impedances for 600 + 1 F and 900 + 2.16 F settings so that an external resistor reference may be used. This option is enabled by setting ZSEXT = 1 (direct Register 108, bit 4). When 600 + 1 F or 900 + 2.16 F impedances are selected, an internal reference resistor is removed from the impedance synthesis circuit to accommodate an external resistor, RZREF, which is inserted into the application circuit as shown in Figure 23.
to TIP C3 R8 STIPAC RZREF Si3215 SRINGAC to RING C4 R9
For 600 + 1 F, RZREF = 12 k and C3, C4 = 100 nF. For 900 + 2.16 F, RZREF = 12 k and C3, C4 = 220 nF.
2.7. Two-Wire Impedance Matching
The ProSLIC provides on-chip, programmable two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. The two-wire impedance is programmed by loading one of the eight available impedance values into the TISS[2:0] bits of the Two-Wire Impedance Synthesis Control register (direct Register 10). If direct Register 10 is not user-defined, the default setting of 600 will be loaded into the TISS register. Real and complex two-wire impedances are realized by internal feedback of a programmable amplifier (RAC) a switched capacitor network (XAC) and a transconductance amplifier (Gm). (See Figure 22.) RAC creates the real portion and XAC creates the imaginary portion of Gm's input. Gm then creates a current that models the desired impedance value to the subscriber loop. The differential ac current is fed to the subscriber loop via the ITIPP and IRINGP pins through an off-chip current buffer (IBUF), which is implemented using transistor Q1 and Q2 (see Figure on page 20). Gm is referenced to an off-chip resistor (R15).
Figure 23. RZREF External Resistor Placement
2.8. Clock Generation
The ProSLIC will generate the necessary internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 768 kHz, 1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined via a counter clocked by PCLK. The three-bit ratio information is automatically transferred into an internal register, PLL_MULT, following a reset of the ProSLIC. The PLL_MULT is used to control the internal PLL, which multiplies PCLK as needed to generate 16.384 MHz rate needed to run the internal filters and other circuitry. The PLL clock synthesizer settles very quickly following powerup. However, the settling time depends on the PCLK frequency, and it can be approximately predicted by the following equation:
64 T SETTLE = ---------------F PCLK
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2.9. Interrupt Logic
The ProSLIC is capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Power alarm Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired Ringing inactive timer expired Pulse metering active timer expired Pulse metering inactive timer expired Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain one bit for each of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource. Three interrupt enable registers also contain one bit for each interrupt function. In the case of the interrupt enable registers, the bits are active high. Refer to the appropriate functional description section for operational details of the interrupt functions. When a resource reaches an interrupt condition, it will signal an interrupt to the interrupt control block. The interrupt control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ will assert low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. To clear a pending interrupt, write the desired bit in the appropriate interrupt status register to 1. Writing a 0 has no effect. This provides a mechanism for clearing individual bits when multiple interrupts occur simultaneously. While the interrupt status registers are non-zero, the INT pin will remain asserted. The first byte of the pair is the command/address byte. The MSB of this byte indicates a register read when 1 and a register write when 0. The remaining seven bits of the command/address byte indicate the address of the register to be accessed. The second byte of the pair is the data byte. Because the falling edge of CS provides resynchronization of the SPI state machine in the event of a framing error, it is recommended (but not required) that CS be taken high between byte transfers as shown in Figures 24 and 25. During a read operation, the SDO becomes active, and the 8-bit contents of the register are driven out MSB first. The SDO will be high impedence on either the falling edge of SCLK following the LSB or the rising of CS as specified by the SPIM bit (direct Register 0, bit 6). SDI is a "don't care" during the data portion of read operations. During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge. The clock should return to a logic high when no transfer is in progress. Indirect registers are accessed through direct registers 29 through 30. Instructions on how to access them are presented in "3.Control Registers" beginning on page 50. There are a number of variations of usage on this fourwire interface:
Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8-`bit transfer (command/address or data). SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tristating its output during the data byte transfer of a read operation. Daisy chain mode. This mode allows communication with banks of up to eight ProSLIC devices using one chip select signal. When the SPIDC bit in the SPI Mode Select register is set, data transfer mode changes to a 3-byte operation: a chip select byte, an address/control byte, and a data byte. Using the circuit shown in Figure 26, a single device may select from the bank of devices by setting the appropriate chip select bit to 1. Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered.
2.10. Serial Peripheral Interface
The control interface to the ProSLIC is a 4-wire interface modeled after commonly-available microcontroller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). Data is transferred a byte at a time with each register access consisting of a pair of byte transfers. Figures 24 and 25 illustrate read and write operation in the SPI bus.
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Don't Care
SCLK
CS
SDI
0
a6
a5
a4
a3
a2
a1
a0
d7
d6
d5
d4
d3
d2
d1
d0
SDO High Impedance
Figure 24. Serial Write 8-Bit Mode
Don't Care
SCLK
CS
SDI
1
a6
a5
a4
a3
a2
a1
a0
Don't Care
SDO
High Impedance
d7
d6
d5
d4
d3
d2
d1
d0
Figure 25. Serial Read 8-Bit Mode
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SDO CPU CS SDI
CS SDO
SDI
SDI0
SDITHRU
CS SDO
SDI
SDI1
SDITHRU
CS SDO
SDI
SDI2
SDITHRU
CS SDO
SDI
SDI3
SDITHRU
Chip Select Byte SCLK
Address Byte
Data Byte
SDI0
C7 C6 C5 C4 C3 C2 C1 C0
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
SDI1
- C7 C6 C5 C4 C3 C2 C1
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
SDI2
- - C7 C6 C5 C4 C3 C2
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
SDI3
- - - C7 C6 C5 C4 C3
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select.
Figure 26. SPI Daisy Chain Mode
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2.11. PCM Interface
The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM Mode Select (direct Register 1), PCM Transmit Start Count (direct registers 2 and 3), and PCM Receive Start Count (direct registers 4 and 5) registers. The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to PCLK frequencies of 256 kHz to 8.192 MHz in power-of-2 increments. (768 kHz and 1.536 MHz are also available.) Timeslots for data transmission and reception are independently configured using the TXS and RXS registers. By setting the correct starting point of the data, the ProSLIC can be configured to support long FSYNC and short FSYNC variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel time slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit. DTX will return to
PCLK
high impedance either on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB. This is based on the setting of the TRI bit of the PCM Mode Select register. Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. In addition to 8-bit data modes, there is a 16-bit mode provided. This mode can be activated via the PCMT bit of the PCM Mode Select register. GCI timing is also supported in which the duration of a data bit is two PCLK cycles. This mode is also activated via the PCM Mode Select register. Setting the TXS or RXS register greater than the number of PCLK cycles in a sample period will stop data transmission because TXS or RXS will never equal the PCLK count. Figures 27-30 illustrate the usage of the PCM highway interface to adapt to common PCM standards.
FSYNC
PCLK_CNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB LSB
DTX
HI-Z MSB LSB
HI-Z
Figure 27. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
PCLK
FSYNC
PCLK_CNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB LSB
DTX
HI-Z MSB LSB
HI-Z
Figure 28. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
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PCLK
FSYNC
PCLK_CNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB LSB
DTX
HI-Z MSB LSB
HI-Z
Figure 29. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
PCLK
FSYNC
PCLK_CNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB LSB
DTX
HI-Z
HI-Z
Figure 30. GCI Example, Timeslot 1 (TXS/RXS = 0)
2.12. Companding
The ProSLIC supports both -255 Law and A-Law companding formats in addition to linear data. These 8-bit companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step bits. -255 Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is selected via the PCMF register. Tables 31 and 32 define the -Law and A-Law encoding formats.
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Table 31. -Law Encode-Decode Characteristics1,2
Segment Number #Intervals X Interval Size Value at Segment Endpoints
8159 . . . 4319 4063 . . . 2143 2015 . . . 1055 991 . . . 511 479 . . . 239 223 . . . 103 95 . . . 35 31 . . . 3 1 0
Digital Code
10000000b
Decode Level
8031
8
16 X 256
10001111b
4191
7
16 X 128
10011111b
2079
6
16 X 64
10101111b
1023
5
16 X 32
10111111b
495
4
16 X 16
11001111b
231
3
16 X 8
11011111b
99
2
16 X 4
11101111b
33
1
15 X 2
__________________ 1X1
11111110b 11111111b
2 0
Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all magnitude bits.
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Table 32. A-Law Encode-Decode Characteristics1,2
Segment Number #intervals X interval size Value at segment endpoints Digital Code Decode Level
7
16 X 128
4096 3968 . . 2176 2048 . . . 1088 1024 . . . 544 512 . . . 272 256 . . . 136 128 . . . 68 64 . . . 2 0
10101010b
4032
10100101b
2112
6
16 X 64
10110101b
1056
5
16 X 32
10000101b
528
4
16 X 16
10010101b
264
3
16 X 8
11100101b
132
2
16 X 4
11110101b
66
32 X 2 1
11010101b
1
Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of all even numbered bits.
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3. Control Registers
Note: Any register not listed here is reserved and must not be written.
Table 33. Direct Register Summary
Register Name Bit 7 Bit 6 Bit 5 Setup Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 1 2 3 4 5 6 8 9 10 11 14 15 18 19 20 21 22 23 28 29 30
SPI Mode Select PCM Mode Select PCM Transmit Start Count--Low Byte PCM Transmit Start Count--High Byte PCM Receive Start Count--Low Byte PCM Receive Start Count--High Byte Part Number Identification Audio Path Loopback Control Audio Gain Control Two-Wire Impedance Synthesis Control Hybrid Control Powerdown Control 1 Powerdown Control 2 Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 Interrupt Enable 1 Interrupt Enable 2 Interrupt Enable 3
SPIDC PNI2
SPIM
PNI[1:0] PCME PCMF[1:0] TXS[7:0]
RNI[3:0] PCMT GCI TRI
TXS[9:8] RXS[7:0] RXS[9:8] PNI[2:0]
Audio
ALM2 RXHP TXHP TXM RXM ATX[1:0] TISE
DLM
ALM1
ARX[1:0] TISS[2:0] HYBA[2:0]
CLC[1:0] HYBP[2:0]
Powerdown
DCOF ADCM
Interrupts
PFR DACM O2IP Q2AP O2IE Q2AE DACON O2AP Q1AP O2AE Q1AE
BIASOF SLICOF GMM O1IP LCIP INDP O1IE LCIE INDE GMON O1AP RTIP O1AE RTIE
ADCON RGAP Q3AP RGAE Q3AE
RGIP Q6AP Q5AP Q4AP RGIE Q6AE Q5AE Q4AE
Indirect Register Access
Indirect Data Access-- Low Byte Indirect Data Access-- High Byte Indirect Address
IDA[7:0] IDA[15:8] IAA[7:0]
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Table 33. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
31 32 33 34 36 37 38 39 40 41 42 43 48 49 50 51 52 63
Indirect Address Status
Oscillators
IAS OSS1 OSS2 RSS REL OZ1 OZ2 RDAC O1TAE O2TAE RTAE O1TIE O2TIE RTIE O1E O2E ROE O1SO[1:0] O2SO[1:0] RVO TSWS
Oscillator 1 Control Oscillator 2 Control Ringing Oscillator Control Oscillator 1 Active Timer--Low Byte Oscillator 1 Active Timer--High Byte Oscillator 1 Inactive Timer--Low Byte Oscillator 1 Inactive Timer--High Byte Oscillator 2 Active Timer--Low Byte Oscillator 2 Active Timer--High Byte Oscillator 2 Inactive Timer--Low Byte Oscillator 2 Inactive Timer--High Byte Ringing Oscillator Active Timer--Low Byte Ringing Oscillator Active Timer--High Byte Ringing Oscillator Inactive Timer--Low Byte Ringing Oscillator Inactive Timer--High Byte FSK Data
OAT1[7:0] OAT1[15:8] OIT1[7:0] OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] FSKDAT
SLIC
Loop Closure Debounce Interval for Automatic Ringing Linefeed Control External Bipolar Transistor Control Battery Feed Control Automatic/Manual Control MNCM MNDIF SQH LFS[2:0] CBY
LCD[7:0]
64 65 66 67
LF[2:0] ETBE VOV SPDS ETBO[1:0] FVBAT AORD AOLD ETBA[1:0] TRACK AOPN
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Table 33. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 92 93 94 95
Loop Closure/Ring Trip Detect Status Loop Closure Debounce Interval Ring Trip Detect Debounce Interval Loop Current Limit On-Hook Line Voltage Common Mode Voltage High Battery Voltage Low Battery Voltage Power Monitor Pointer Line Power Output Monitor Loop Voltage Sense Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 Battery Voltage Sense 2 Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense DC-DC Converter PWM Period DC-DC Converter Switch- DCCAL ing Delay PWM Pulse Width Reserved DCPOL DCPW[7:0] LVSP LCSP VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0] DCN[7:0] PWROM[7:0] VSGN
DBIRAW LCDI[6:0] RTDI[6:0]
RTP
LCR
ILIM[2:0] VOC[5:0] VCM[5:0] VBATH[5:0] VBATL[5:0] PWRMP[2:0]
LVS[5:0] LCS[5:0]
DCTOF[4:0]
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Table 33. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
96 97 98 99 100
Calibration Control/ Status Register 1 Calibration Control/ Status Register 2 RING Gain Mismatch Calibration Result TIP Gain Mismatch Calibration Result Differential Loop Current Gain Calibration Result Common Mode Loop Current Gain Calibration Result Current Limit Calibration Result Monitor ADC Offset Calibration Result Analog DAC/ADC Offset DAC Offset Calibration Result DC Peak Current Monitor Calibration Result Enhancement Enable
CAL
CALSP
CALR
CALM1
CALT
CALM2
CALD
CALDAC
CALC
CALADC
CALIL
CALCM
CALGMR[4:0] CALGMT[4:0] CALGD[4:0]
101
CALGC[4:0]
102 103 104 105 107 108
CALGIL[3:0] CALMG1[3:0] DACP DACOF[7:0] CMDCPK[3:0] ILIMEN FSKEN DCSU LCVE DCFIL HYSTEN CALMG2[3:0] DACN ADCP ADCN
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Register 0. SPI Mode Select Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
SPIDC R/W
SPIM R/W
PNI[1:0] R
RNI[3:0] R
Reset settings = 00xx_xxxx
Bit Name Function SPI Daisy Chain Mode Enable. 0 = Disable SPI daisy chain mode. 1 = Enable SPI daisy chain mode. SPI Mode. 0 = Causes SDO to tri-state on rising edge of SCLK of LSB. 1 = Normal operation; SDO tri-states on rising edge of CS. Part Number Identification. 00 = Si3215 01 = Unused 10 = Unused 11 = Si3215M Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc.
7
SPIDC
6
SPIM
5:4
PNI[1:0]
3:0
RNI[3:0]
54
Rev. 0.92
Si3215
Register 1. PCM Mode Select Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
PNI2 R
PCME R/W
PCMF[1:0] R/W
PCMT R/W
GCI R/W
TRI R/W
Reset settings = 1000_1000
Bit 7 Name PNI2 Function Part Number Identification 2. 0 = Si3210 family 1 = Si3215 family Read returns zero. PCM Enable. 0 = Disable PCM transfers. 1 = Enable PCM transfers. PCM Format. 00 = A-Law 01 = -Law 10 = Reserved 11 = Linear PCM Transfer Size. 0 = 8-bit transfer. 1 = 16-bit transfer. GCI Clock Format. 0 = 1 PCLK per data bit. 1 = 2 PCLKs per data bit. Tri-state Bit 0. 0 = Tri-state bit 0 on positive edge of PCLK. 1 = Tri-state bit 0 on negative edge of PCLK.
6 5
Reserved PCME
4:3
PCMF[1:0]
2
PCMT
1
GCI
0
TRI
Register 2. PCM Transmit Start Count--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
TXS[7:0] R/W
Reset settings = 0000_0000
Bit Name Function PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 27 on page 46.
7:0
TXS[7:0]
Rev. 0.92
55
Si3215
Register 3. PCM Transmit Start Count--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
TXS[9:8] R/W
Reset settings = 0000_0000
Bit Name Function
7:2 1:0
Reserved TXS[9:8]
Read returns zero.
PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 27 on page 46.
Register 4. PCM Receive Start Count--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RXS[7:0] R/W
Reset settings = 0000_0000
Bit Name Function PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 27 on page 46.
7:0
RXS[7:0]
Register 5. PCM Receive Start Count--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RXS[9:8] R/W
Reset settings = 0000_0000
Bit Name Function
7:2 1:0
Reserved RXS[9:8]
Read returns zero.
PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 27 on page 46.
56
Rev. 0.92
Si3215
Register 6. Part Number Identification Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
PNI[2:0] R
Reset settings = 0xx0_0000
Bit Name Function Part Number Identification.
Note: PNI[2] can be read in direct Register 1. PNI[1:0] can be read in direct Register 0.
7:5
PNI[2:0]
000 = Si3215 001 = Reserved 010 = Reserved 011 = Si3215M 4:0 Reserved Read returns zero.
100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved
Register 8. Audio Path Loopback Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
ALM2 R/W
DLM R/W
ALM1 R/W
Reset settings = 0000_0010
Bit Name Function
7:3 2
Reserved ALM2
Read returns zero.
Analog Loopback Mode 2. (See Figure 22 on page 40.) 0 = Full analog loopback mode disabled. 1 = Full analog loopback mode enabled. Digital Loopback Mode. (See Figure 22 on page 40.) 0 = Digital loopback disabled. 1 = Digital loopback enabled. Analog Loopback Mode 1. (See Figure 22 on page 40.) 0 = Analog loopback disabled. 1 = Analog loopback enabled.
1
DLM
0
ALM1
Rev. 0.92
57
Si3215
Register 9. Audio Gain Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RXHP R/W
TXHP R/W
TXM R/W
RXM R/W
ATX[1:0] R/W
ARX[1:0] R/W
Reset settings = 0000_0000
Bit Name Function Receive Path High Pass Filter Disable. 0 = HPF enabled in receive path, RHDF. 1 = HPF bypassed in receive path, RHDF. Transmit Path High Pass Filter Disable. 0 = HPF enabled in transmit path, THPF. 1 = HPF bypassed in transmit path, THPF. Transmit Path Mute. Refer to position of digital mute in Figure 22 on page 40. 0 = Transmit signal passed. 1 = Transmit signal muted. Receive Path Mute. Refer to position of digital mute in Figure 22 on page 40. 0 = Receive signal passed. 1 = Receive signal muted. Analog Transmit Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = ATX gain = 0 dB; analog transmit path muted. Analog Receive Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = Analog receive path muted.
7
RXHP
6
TXHP
5
TXM
4
RXM
3:2
ATX[1:0]
1:0
ARX[1:0]
58
Rev. 0.92
Si3215
Register 10. Two-Wire Impedance Synthesis Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CLC[1:0] R/W
TISE R/W
TISS[2:0] R/W
Reset settings = 0000_1000
Bit Name Function
7:6 5:4
Reserved CLC[1:0]
Read returns zero.
Line Capacitance Compensation. 00 = Off 01 = 4.7 nF 10 = 10 nF 11 = Reserved Two-Wire Impedance Synthesis Enable. 0 = Two-wire impedance synthesis disabled. 1 = Two-wire impedance synthesis enabled. Two-Wire Impedance Synthesis Selection. 000 = 600 001 = 900 010 = Japan (600 + 1 F); requires external resistor RZREF = 12 k and C3, C4 = 100 nF. 011 = 900 + 2.16 F; requires external resistor RZREF = 18 k and C3, C4 = 220 nF. 100 = CTR21 270 + (750 || 150 nF) 101 = Australia/New Zealand 220 + (820 || 120 nF) 110 = Slovakia/Slovenia/South Africa 220 + (820 || 115 nF) 111 = China 200 + (680 || 100 nF)
3
TISE
2:0
TISS[2:0]
Rev. 0.92
59
Si3215
Register 11. Hybrid Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
HYBP[2:0] R/W
HYBA[2:0] R/W
Reset settings = 0011_0011
Bit Name Function
7 6:4
Reserved HYBP[2:0]
Read returns zero.
Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off
3 2:0
Reserved HYBA[2:0]
Read returns zero.
Audio Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off
60
Rev. 0.92
Si3215
Register 14. Powerdown Control 1 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
DCOF R/W
PFR R/W
BIASOF R/W
SLICOF R/W
Reset settings = 0001_0000
Bit Name Function
7:5 4
Reserved DCOF
Read returns zero.
DC-DC Converter Power-Off Control 0 = Automatic power control. 1 = Override automatic control and force dc-dc circuitry off. PLL Free-Run Control. 0 = Automatic free-run control. 1 = Override automatic control and force PLL into free-run state.
3
PFR
2 1
Reserved BIASOF
Read returns zero.
DC Bias Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force dc bias circuitry off. SLIC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force SLIC circuitry off.
0
SLICOF
Rev. 0.92
61
Si3215
Register 15. Powerdown Control 2 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
ADCM R/W
ADCON R/W
DACM R/W
DACON R/W
GMM R/W
GMON R/W
Reset settings = 0000_0000
Bit Name Function
7:6 5
Reserved ADCM
Read returns zero.
Analog to Digital Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; ADCON controls on/off state. Analog to Digital Converter On/Off Power Control. When ADCM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. ADCON has no effect when ADCM = 0. Digital to Analog Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; DACON controls on/off state. Digital to Analog Converter On/Off Power Control. When DACM = 1: 0 = Digital to analog converter powered off. 1 = Digital to analog converter powered on. DACON has no effect when DACM = 0. Transconductance Amplifier Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; GMON controls on/off state. Transconductance Amplifier On/Off Power Control. When GMM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. GMON has no effect when GMM = 0.
4
ADCON
3
DACM
2
DACON
1
GMM
0
GMON
62
Rev. 0.92
Si3215
Register 18. Interrupt Status 1 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RGIP R/W
RGAP R/W
O2IP R/W
O2AP R/W
O1IP R/W
O1AP R/W
Reset settings = 0000_0000
Bit Name Function
7:6 5
Reserved RGIP
Read returns zero.
Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
4
RGAP
3
O2IP
2
O2AP
1
O1IP
0
O1AP
Rev. 0.92
63
Si3215
Register 19. Interrupt Status 2 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
Q6AP R/W
Q5AP R/W
Q4AP R/W
Q3AP R/W
Q2AP R/W
Q1AP R/W
LCIP R/W
RTIP R/W
Reset settings = 0000_0000
Bit Name Function Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q4 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q3 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q2 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q1 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Loop Closure Transition Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ring Trip Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
7
Q6AP
6
Q5AP
5
Q4AP
4
Q3AP
3
Q2AP
2
Q1AP
1
LCIP
0
RTIP
64
Rev. 0.92
Si3215
Register 20. Interrupt Status 3 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
INDP R/W
Reset settings = 0000_0000
Bit Name Function
7:2 1
Reserved INDP
Read returns zero.
Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
0
Reserved
Read returns zero.
Rev. 0.92
65
Si3215
Register 21. Interrupt Enable 1 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RGIE R/W
RGAE R/W
O2IE R/W
O2AE R/W
O1IE R/W
O1AE R/W
Reset settings = 0000_0000
Bit Name Function
7:6 5
Reserved RGIE
Read returns zero.
Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
4
RGAE
3
O2IE
2
O2AE
1
O1IE
0
O1AE
66
Rev. 0.92
Si3215
Register 22. Interrupt Enable 2 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
Q6AE R/W
Q5AE R/W
Q4AE R/W
Q3AE R/W
Q2AE R/W
Q1AE R/W
LCIE R/W
RTIE R/W
Reset settings = 0000_0000
Bit Name Function Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q3 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q2 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q1 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Loop Closure Transition Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ring Trip Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
7
Q6AE
6
Q5AE
5
Q4AE
4
Q3AE
3
Q2AE
2
Q1AE
1
LCIE
0
RTIE
Rev. 0.92
67
Si3215
Register 23. Interrupt Enable 3 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
INDE R/W
Reset settings = 0000_0000
Bit Name Function
7:2 1
Reserved INDE
Read returns zero.
Indirect Register Access Serviced Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
0
Reserved
Read returns zero.
68
Rev. 0.92
Si3215
Register 28. Indirect Data Access--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IDA[7:0] R/W
Reset settings = 0000_0000
Bit Name Function Indirect Data Access--Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation).
7:0
IDA[7:0]
Register 29. Indirect Data Access--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IDA[15:8] R/W
Reset settings = 0000_0000
Bit Name Function Indirect Data Access--High Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation).
7:0
IDA[15:8]
Rev. 0.92
69
Si3215
Register 30. Indirect Address Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IAA[7:0] R/W
Reset settings = xxxx_xxxx
Bit Name Function Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation).
7:0
IAA[7:0]
Register 31. Indirect Address Status Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IAS R
Reset settings = 0000_0000
Bit Name Function
7:1 0
Reserved IAS
Read returns zero.
Indirect Access Status. 0 = No indirect memory access pending. 1 = Indirect memory access pending.
70
Rev. 0.92
Si3215
Register 32. Oscillator 1 Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OSS1 R
REL R/W
OZ1 R/W
O1TAE R/W
O1TIE R/W
O1E R/W
O1SO[1:0] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 1 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling. 0 = Oscillator 1 will stop signaling after inactive timer expires. 1 = Oscillator 1 will continue to read register parameters and output signals. Oscillator 1 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing after active timer expires. Oscillator 1 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 1 Signal Output Routing. 00 = Unassigned path (output not connected). 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths.
7
OSS1
6
REL
5
OZ1
4
O1TAE
3
O1TIE
2
O1E
1:0
O1SO[1:0]
Rev. 0.92
71
Si3215
Register 33. Oscillator 2 Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OSS2 R
OZ2 R/W
O2TAE R/W
O2TIE R/W
O2E R/W
O2SO[1:0] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 2 Signal Status. 0 = Output signal inactive. 1 = Output signal active.
7
OSS2
6 5
Reserved OZ2
Read returns zero.
Oscillator 2 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing. Oscillator 2 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 2 Signal Output Routing. 00 = Unassigned path (output not connected) 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths.
4
O2TAE
3
O2TIE
2
O2E
1:0
O2SO[1:0]
72
Rev. 0.92
Si3215
Register 34. Ringing Oscillator Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RSS R
RDAC R
RTAE R/W
RTIE R/W
ROE R
RVO R/W
TSWS R/W
Reset settings = 0000_0000
Bit Name Function Ringing Signal Status. 0 = Ringing oscillator output signal inactive. 1 = Ringing oscillator output signal active.
7
RSS
6 5
Reserved RDAC
Read returns zero.
Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure continuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at TIP and RING. 0 = Ringing signal not present at TIP and RING. 1 = Ringing signal present at TIP and RING. Ringing Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Oscillator Enable. 0 = Ringing oscillator disabled. 1 = Ringing oscillator enabled. Ringing Voltage Offset. 0 = No dc offset added to ringing signal. 1 = DC offset added to ringing signal. Trapezoid/Sinusoid Waveshape Select. 0 = Sinusoid 1 = Trapezoid
4
RTAE
3
RTIE
2
ROE
1
RVO
0
TSWS
Rev. 0.92
73
Si3215
Register 36. Oscillator 1 Active Timer--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OAT1[7:0] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 1 Active Timer. LSB = 125 s
7:0
OAT1[7:0]
Register 37. Oscillator 1 Active Timer--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OAT1[15:8] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 1 Active Timer.
7:0
OAT1[15:8]
Register 38. Oscillator 1 Inactive Timer--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OIT1[7:0] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 1 Inactive Timer. LSB = 125 s
7:0
OIT1[7:0]
74
Rev. 0.92
Si3215
Register 39. Oscillator 1 Inactive Timer--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OIT1[15:8] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 1 Inactive Timer.
7:0
OIT1[15:8]
Register 40. Oscillator 2 Active Timer--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OAT2[7:0] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 2 Active Timer. LSB = 125 s
7:0
OAT2[7:0]
Register 41. Oscillator 2 Active Timer--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OAT2[15:8] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 2 Active Timer.
7:0
OAT2[15:8]
Rev. 0.92
75
Si3215
Register 42. Oscillator 2 Inactive Timer--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OIT2[7:0] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 2 Inactive Timer. LSB = 125 s
7:0
OIT2[7:0]
Register 43. Oscillator 2 Inactive Timer--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
OIT2[15:8] R/W
Reset settings = 0000_0000
Bit Name Function Oscillator 2 Inactive Timer.
7:0
OIT2[15:8]
Register 48. Ringing Oscillator Active Timer--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RAT[7:0] R/W
Reset settings = 0000_0000
Bit Name Function Ringing Active Timer. LSB = 125 s
7:0
RAT[7:0]
76
Rev. 0.92
Si3215
Register 49. Ringing Oscillator Active Timer--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RAT[15:8] R/W
Reset settings = 0000_0000
Bit Name Function Ringing Active Timer.
7:0
RAT[15:8]
Register 50. Ringing Oscillator Inactive Timer--Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RIT[7:0] R/W
Reset settings = 0000_0000
Bit Name Function Ringing Inactive Timer. LSB = 125 s
7:0
RIT[7:0]
Register 51. Ringing Oscillator Inactive Timer--High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RIT[15:8] R/W
Reset settings = 0000_0000
Bit Name Function Ringing Inactive Timer.
7:0
RIT[15:8]
Rev. 0.92
77
Si3215
Register 52. FSK Data Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
FSKDAT R/W
Reset settings = 0000_0000
Bit Name Function
7:1 0
Reserved FSKDAT
Read returns zero.
FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data.
Register 63. Loop Closure Debounce Interval Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
LCD[7:0]
Reset settings = 0101_0100
Bit Name Function Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps.
7:0
LCD[7:0]
78
Rev. 0.92
Si3215
Register 64. Linefeed Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
LFS[2:0] R
LF[2:0] R/W
Reset settings = 0000_0000
Bit Name Function
7 6:4
Reserved LFS[2:0]
Read returns zero.
Linefeed Shadow. This register reflects the actual real time linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g., when linefeed equals ringing state, LFS will equal on-hook transmission state during ringing silent period and ringing state during ring burst). 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open
3 2:0
Reserved LF[2:0]
Read returns zero.
Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open
Rev. 0.92
79
Si3215
Register 65. External Bipolar Transistor Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
SQH R/W
CBY R/W
ETBE R/W
ETBO[1:0] R/W
ETBA[1:0] R/W
Reset settings = 0110_0001
Bit Name Function
7 6
Reserved SQH
Read returns zero.
Audio Squelch. 0 = No squelch. 1 = STIPAC and SRINGAC pins squelched. Capacitor Bypass. 0 = Capacitors CP (C1) and CM (C2) in circuit. 1 = Capacitors CP (C1) and CM (C2) bypassed. External Transistor Bias Enable. 0 = Bias disabled. 1 = Bias enabled. External Transistor Bias Levels--On-Hook Transmission State. DC bias current which flows through external BJTs in the on-hook transmission state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved External Transistor Bias Levels--Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved
5
CBY
4
ETBE
3:2
ETBO[1:0]
1:0
ETBA[1:0]
80
Rev. 0.92
Si3215
Register 66. Battery Feed Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VOV R/W
FVBAT R/W
TRACK R/W
Reset settings = 0000_0011
Bit Name Function
7:5 4
Reserved VOV
Read returns zero.
Overhead Voltage Range Increase. This bit selects the programmable range for VOV, which is defined in indirect Register 64. 0 = VOV = 0 V to 9 V 1 = VOV = 0 V to 13.5 V VBAT Manual Setting.
3
FVBAT
0 = Normal operation 1 = VBAT tracks VBATH register. 2:1 0 Reserved TRACK Read returns zero.
DC-DC Converter Tracking Mode. 0 = |VBAT| will not decrease below VBATL. 1 = VBAT tracks VRING.
Rev. 0.92
81
Si3215
Register 67. Automatic/Manual Control Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
MNCM R/W
MNDIF R/W
SPDS R/W
AORD R/W
AOLD R/W
AOPN R/W
Reset settings = 0001_1111
Bit Name Function
7 6
Reserved MNCM
Read returns zero.
Common Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. Differential Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control (forces differential voltage to follow VOC value). Speed-Up Mode Enable. 0 = Speed-up disabled. 1 = Automatic speed-up.
5
MNDIF
4
SPDS
3 2
Reserved AORD
Read returns zero.
Automatic/Manual Ring Trip Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon ring trip detect. Automatic/Manual Loop Closure Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon loop closure detect. Power Alarm Automatic/Manual Detect. 0 = Manual mode. 1 = Enter open state automatically upon power alarm.
1
AOLD
0
AOPN
82
Rev. 0.92
Si3215
Register 68. Loop Closure/Ring Trip Detect Status Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
DBIRAW R
RTP R
LCR R
Reset settings = 0000_0000
Bit Name Function
7:3 2
Reserved DBIRAW
Read returns zero.
Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the real time output of ring trip and loop closure detect circuits before debouncing. 0 = Ring trip/loop closure threshold exceeded. 1 = Ring trip/loop closure threshold not exceeded. Ring Trip Detect Indicator (Filtered Output). 0 = Ring trip detect has not occurred. 1 = Ring trip detect occurred. Loop Closure Detect Indicator (Filtered Output). 0 = Loop closure detect has not occurred. 1 = Loop closure detect has occurred.
1
RTP
0
LCR
Register 69. Loop Closure Debounce Interval Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
LCDI[6:0] R/W
Reset settings = 0000_1010
Bit Name Function
7 6:0
Reserved LCDI[6:0]
Read returns zero.
Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms.
Rev. 0.92
83
Si3215
Register 70. Ring Trip Detect Debounce Interval Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
RTDI[6:0] R/W
Reset settings = 0000_1010
Bit Name Function
7 6:0
Reserved RTDI[6:0]
Read returns zero.
Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms.
Register 71. Loop Current Limit Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
ILIM[2:0] R/W
Reset settings = 0000_0000
Bit Name Function
7:3 2:0
Reserved ILIM[2:0]
Read returns zero.
Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps.
84
Rev. 0.92
Si3215
Register 72. On-Hook Line Voltage Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VSGN R/W
VOC[5:0] R/W
Reset settings = 0010_0000
Bit Name Function
7 6
Reserved VSGN
Read returns zero.
On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity (VTIP-VRING). 0 = VTIP-VRINGis positive 1 = VTIP-VRING is negative On-Hook Line Voltage. The value written to this register sets the on-hook line voltage (VTIP-VRING). Value may be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V.
5:0
VOC[5:0]
Register 73. Common Mode Voltage Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VCM[5:0] R/W
Reset settings = 0000_0010
Bit Name Function
7:6 5:0
Reserved VCM[5:0]
Read returns zero.
Common Mode Voltage. The value written to this register sets VTIP for forward active and forward on-hook transmission states and VRING for reverse active and reverse on-hook transmission states. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -3 V.
Rev. 0.92
85
Si3215
Register 74. High Battery Voltage Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VBATH[5:0] R/W
Reset settings = 0011_0010
Bit Name Function
7:6 5:0
Reserved VBATH[5:0]
Read returns zero.
High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -75 V. For Si3211, VBATH must be set equal to externally supplied VBATH input voltage.
Register 75. Low Battery Voltage Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VBATL[5:0] R/W
Reset settings = 0001_0000
Bit Name Function
7:6 5:0
Reserved VBATL[5:0]
Read returns zero.
Low Battery Voltage. The value written to this register sets low battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -24 V. For Si3211, VBATL must be set equal to externally supplied VBATL input voltage.
86
Rev. 0.92
Si3215
Register 76. Power Monitor Pointer Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
PWRMP[2:0] R/W
Reset settings = 0000_0000
Bit Name Function
7:3 2:0
Reserved PWRMP[2:0]
Read returns zero.
Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. 000 = Q1 001 = Q2 010 = Q3 011 = Q4 100 = Q5 101 = Q6 110 = Undefined 111 = Undefined
Register 77. Line Power Output Monitor Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
PWROM[7:0] R
Reset settings = 0000_0000
Bit Name Function Line Power Output Monitor. This register reports the real time power output of the transistor selected using PWRMP. The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6. The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4.
7:0
PWROM[7:0]
Rev. 0.92
87
Si3215
Register 78. Loop Voltage Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
LVSP R
LVS[5:0] R
Reset settings = 0000_0000
Bit Name Function
7 6
Reserved LVSP
Read returns zero.
Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (VTIP - VRING). 0 = Positive loop voltage (VTIP > VRING). 1 = Negative loop voltage (VTIP < VRING). Loop Voltage Sense Magnitude. This register reports the magnitude of the differential loop voltage (VTIP-VRING). The range is 0 V to 94.5 V in 1.5 V steps.
5:0
LVS[5:0]
Register 79. Loop Current Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
LCSP R
LCS[5:0] R
Reset settings = 0000_0000
Bit Name Function
7 6
Reserved LCSP
Read returns zero.
Loop Current Sense Polarity. This register reports the polarity of the loop current. 0 = Positive loop current (forward direction). 1 = Negative loop current (reverse direction). Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in 1.25 mA steps.
5:0
LCS[5:0]
88
Rev. 0.92
Si3215
Register 80. TIP Voltage Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VTIP[7:0] R
Reset settings = 0000_0000
Bit Name Function TIP Voltage Sense. This register reports the real time voltage at TIP with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps.
7:0
VTIP[7:0]
Register 81. RING Voltage Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VRING[7:0] R
Reset settings = 0000_0000
Bit Name Function RING Voltage Sense. This register reports the real time voltage at RING with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps.
7:0
VRING[7:0]
Register 82. Battery Voltage Sense 1 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VBATS1[7:0] R
Reset settings = 0000_0000
Bit Name Function Battery Voltage Sense 1. This register is one of two registers that reports the real time voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps.
7:0
VBATS1[7:0]
Rev. 0.92
89
Si3215
Register 83. Battery Voltage Sense 2 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
VBATS2[7:0] R
Reset settings = 0000_0000
Bit Name Function Battery Voltage Sense 2. This register is one of two registers that reports the real time voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps.
7:0
VBATS2[7:0]
Register 84. Transistor 1 Current Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IQ1[7:0] R
Reset settings = xxxx_xxxx
Bit Name Function Transistor 1 Current Sense. This register reports the real time current through Q1. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current.
7:0
IQ1[7:0]
Register 85. Transistor 2 Current Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IQ2[7:0] R
Reset settings = xxxx_xxxx
Bit Name Function Transistor 2 Current Sense. This register reports the real time current through Q2. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current.
7:0
IQ2[7:0]
90
Rev. 0.92
Si3215
Register 86. Transistor 3 Current Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IQ3[7:0] R
Reset settings = xxxx_xxxx
Bit Name Function Transistor 3 Current Sense. This register reports the real time current through Q3. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 A steps.
7:0
IQ3[7:0]
Register 87. Transistor 4 Current Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IQ4[7:0] R
Reset settings = xxxx_xxxx
Bit Name Function Transistor 4 Current Sense. This register reports the real time current through Q4. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 A steps.
7:0
IQ4[7:0]
Register 88. Transistor 5 Current Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IQ5[7:0] R
Reset settings = xxxx_xxxx
Bit Name Function Transistor 5 Current Sense. This register reports the real time current through Q5. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps.
7:0
IQ5[7:0]
Rev. 0.92
91
Si3215
Register 89. Transistor 6 Current Sense Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
IQ6[7:0] R
Reset settings = xxxx_xxxx
Bit Name Function Transistor 6 Current Sense. This register reports the real time current through Q6. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps.
7:0
IQ6[7:0]
Register 92. DC-DC Converter PWM Period Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
DCN[7] R/W
1 R
DCN[5:0] R/W
Reset settings = 1111_1111
Bit Name Function DC-DC Converter Period. This register sets the PWM period for the dc-dc converter. The range is 3.906 s (0x40) to 15.564 s (0xFF) in 61.035 ns steps. Bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906-7.751 s, used for MOSFET transistor switching. 11.719-15.564 s, used for BJT transistor switching.
7:0
DCN[7:0]
92
Rev. 0.92
Si3215
Register 93. DC-DC Converter Switching Delay Si3215 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
DCCAL R/W
DCPOL R
DCTOF[4:0] R/W
Reset settings = 0001_0100 (Si3215) Reset settings = 0011_0100 (Si3215M)
Bit Name Function DC-DC Converter Peak Current Monitor Calibration Status. Writing a one to this bit starts the dc-dc converter peak current monitor calibration routine. 0 = Normal operation. 1 = Calibration being performed.
7
DCCAL
6 5
Reserved DCPOL
Read returns zero.
DC-DC Converter Feed Forward Pin (DCFF) Polarity. This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3215 are offered to support the two relationships. 0 = DCFF pin polarity is opposite of DCDRV pin (Si3215). 1 = DCFF pin polarity is same as DCDRV pin (Si3215M). DC-DC Converter Minimum Off Time. This register sets the minimum off time for the pulse width modulated dc-dc converter control. TOFF = (DCTOF + 4) 61.035 ns.
4:0
DCTOF[4:0]
Rev. 0.92
93
Si3215
Register 94. DC-DC Converter PWM Pulse Width Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
DCPW[7:0] R
Reset settings = 0000_0000
Bit Name Function DC-DC Converter Pulse Width. Pulse width of DCDRV is given by PW = (DCPW - DCTOF - 4) x 61.035 ns.
7:0
DCPW[7:0]
94
Rev. 0.92
Si3215
Register 96. Calibration Control/Status Register 1 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CAL R/W
CALSP R/W
CALR R/W
CALT R/W
CALD R/W
CALC R/W
CALIL R/W
Reset settings = 0001_1111
Bit Name Function
7 6
Reserved CAL
Read returns zero.
Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 = Normal operation or calibration complete. 1 = Calibration in progress. Calibration Speedup. Setting this bit shortens the time allotted for VBAT settling at the beginning of the calibration cycle. 0 = 300 ms 1 = 30 ms RING Gain Mismatch Calibration. For use with discrete solution only. When using the Si3201, consult "AN35: Si321x User's Quick Reference Guide" and follow instructions for manual calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Gain Mismatch Calibration. For use with discrete solution only. When using the Si3201, consult "AN35: Si321x User's Quick Reference Guide" and follow instructions for manual calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Differential DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ILIM Calibration.
5
CALSP
4
CALR
3
CALT
2
CALD
1
CALC
0
CALIL
0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress.
Rev. 0.92
95
Si3215
Register 97. Calibration Control/Status Register 2 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CALM1 R/W
CALM2 R/W
CALDAC R/W
CALADC R/W
CALCM R/W
Reset settings = 0001_1111
Bit Name Function
7:5 4
Reserved CALM1
Read returns zero.
Monitor ADC Calibration 1. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Monitor ADC Calibration 2. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. DAC Calibration. Setting this bit begins calibration of the audio DAC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ADC Calibration. Setting this bit begins calibration of the audio ADC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode Balance Calibration. Setting this bit begins calibration of the ac longitudinal balance. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress.
3
CALM2
2
CALDAC
1
CALADC
0
CALCM
96
Rev. 0.92
Si3215
Register 98. RING Gain Mismatch Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CALGMR[4:0] R/W
Reset settings = 0001_0000
Bit Name Function
7:5 4:0
Reserved CALGMR[4:0]
Read returns zero.
Gain Mismatch of IE Tracking Loop for RING Current.
Register 99. TIP Gain Mismatch Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CALGMT[4:0] R/W
Reset settings = 0001_0000
Bit Name Function
7:5 4:0
Reserved CALGMT[4:0]
Read returns zero.
Gain Mismatch of IE Tracking Loop for TIP Current.
Register 100. Differential Loop Current Gain Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CALGD[4:0] R/W
Reset settings = 0001_0001
Bit Name Function
7:5 4:0
Reserved CALGD[4:0]
Read returns zero.
Differential DAC Gain Calibration Result.
Rev. 0.92
97
Si3215
Register 101. Common Mode Loop Current Gain Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CALGC[4:0] R/W
Reset settings = 0001_0001
Bit Name Function
7:5 4:0
Reserved CALGC[4:0]
Read returns zero.
Common Mode DAC Gain Calibration Result.
Register 102. Current Limit Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CALGIL[3:0] R/W
Reset settings = 0000_1000
Bit Name Function
7:5 3:0
Reserved CALGIL[3:0]
Read returns zero.
Current Limit Calibration Result.
Register 103. Monitor ADC Offset Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CALMG1[3:0] R/W
CALMG2[3:0] R/W
Reset settings = 1000_1000
Bit Name Function Monitor ADC Offset Calibration Result 1. Monitor ADC Offset Calibration Result 2.
7:4 3:0
CALMG1[3:0] CALMG2[3:0]
98
Rev. 0.92
Si3215
Register 104. Analog DAC/ADC Offset Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
DACP R/W
DACN R/W
ADCP R/W
ADCN R/W
Reset settings = 0000_0000
Bit Name Function
7:4 3 2 1 0
Reserved DACP DACN ADCP ADCN
Read returns zero.
Positive Analog DAC Offset. Negative Analog DAC Offset. Positive Analog ADC Offset. Negative Analog ADC Offset.
Register 105. DAC Offset Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
DACOF[7:0] R/W
Reset settings = 0000_0000
Bit Name Function DAC Offset Calibration Result.
7:0
DACOF[7:0]
Register 107. DC Peak Current Monitor Calibration Result Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
CMDCPK[3:0] R/W
Reset settings = 0000_1000
Bit Name Function
7:4 3:0
Reserved CMDCPK[3:0]
Read returns zero.
DC Peak Current Monitor Calibration Result.
Rev. 0.92
99
Si3215
Register 108. Enhancement Enable Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
ILIMEN R/W
FSKEN R/W
DCSU R/W
LCVE R/W
DCFIL R/W
HYSTEN R/W
Reset settings = 0000_0000
Bit Name Function Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time to a dc linefeed state. 0 = The value programmed in ILIM (direct Register 71) is used. 1 = The maximum differential loop current limit is temporarily increased to 41 mA. FSK Generation Enhancement. When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are used for FSK generation (indirect registers 69-74). Audio tones are generated using this new higher frequency, and oscillator 1 active and inactive timers have a finer bit resolution of 41.67 s. This provides greater resolution during FSK caller ID signal generation. 0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always used. 1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only when REL = 1; otherwise clocked at 8 kHz. DC-DC Converter Control Speedup. When enabled, this bit invokes a multi-threshold error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes. 0 = Normal control algorithm used. 1 = Multi-threshold error control algorithm used.
7
ILIMEN
6
FSKEN
5
DCSU
4:3 2
Reserved LCVE
Read returns zero.
Voltage-Based Loop Closure. Enables loop closure to be determined by the TIP-to-RING voltage rather than loop current. 0 = Loop closure determined by loop current. 1 = Loop closure determined by TIP-to-RING voltage. DC-DC Converter Squelch. When enabled, this bit squelches noise in the audio band from the dc-dc converter control loop. 0 = Voice band squelch disabled. 1 = Voice band squelch enabled. Loop Closure Hysteresis Enable. When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by indirect registers 15 and 66, respectively. 0 = Loop closure hysteresis disabled. 1 = Loop closure hysteresis enabled.
1
DCFIL
0
HYSTEN
100
Rev. 0.92
Si3215
4. Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update. A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of 16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
Table 34. Si3210 to Si3215 Indirect Register Cross Reference
Si3210 Indirect Register Si3215 Indirect Register Indirect Register Name Si3210 Indirect Register Si3215 Indirect Register Indirect Register Name Si3210 Indirect Register Si3215 Indirect Register Indirect Register Name
13 14 15 16 17 18 19 20 21 22 26
0 1 2 3 4 5 6 7 8 9 13
OSC1 OSC1X OSC1Y OSC2 OSC2X OSC2Y ROFF RCO RNGX RNGY DACG
27 28 29 30 31 32 33 34 35 36 37
14 15 16 17 18 19 20 21 22 23 24
ADCG LCRT RPTP CML CMH PPT12 PPT34 PPT56 NCLR NRTP NQ12
38 39 40 41 43 99 100 101 102 103 104
25 26 27 64 66 69 70 71 72 73 74
NQ34 NQ56 VCMR VMIND LCRTL FSK0X FSK0 FSK1X FSK1 FSK01 FSK10
Rev. 0.92
101
Si3215
4.1. Oscillators
See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 35. Oscillator Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 2 3 4 5 6 7 8 9 ROFF[5:0]
OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OSC2[15:0] OSC2X[15:0] OSC2Y[15:0]
RCO[15:0] RNGX[15:0] RNGY[15:0]
Table 36. Oscillator Indirect Registers Description
Address Description Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. Sets initial phase of tone generator 1 signal. Oscillator 2 Frequency Coefficient. Sets tone generator 2 frequency. Oscillator 2 Amplitude Register. Sets tone generator 2 signal amplitude. Oscillator 2 Initial Phase Register. Sets initial phase of tone generator 2 signal. Ringing Oscillator DC Offset. Sets dc offset component (VTIP-VRING) to ringing waveform. The range is 0 to 94.5 V in 1.5 V increments. Reference Page
0 1 2 3 4 5 6
33 33 33 33 33 33 35
102
Rev. 0.92
Si3215
Table 36. Oscillator Indirect Registers Description (Continued)
Address Description Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator signal. Reference Page
7 8 9
35 35 35
4.2. Digital Programmable Gain/Attenuation
See functional description sections of digital programmable gain/attenuation for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 37. Digital Programmable Gain/Attenuation Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
13 14
DACG[11:0] ADCG[11:0]
Table 38. Digital Programmable Gain/Attenuation Indirect Registers Description
Addr. Description Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively multiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to - dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Transmit Path Analog to Digital Converter Gain/Attenuation. This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to - dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Reference Page
13
39
14
39
Rev. 0.92
103
Si3215
4.3. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 39. SLIC Control Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15 16 17 18 19 20 21 22 23 24 25 26 27 64 66
LCRT[5:0] RPTP[5:0] CML[5:0] CMH[5:0] PPT12[7:0] PPT34[7:0] PPT56[7:0] NCLR[12:0] NRTP[12:0] NQ12[12:0] NQ34[12:0] NQ56[12:0] VCMR[3:0] VMIND[3:0] LCRTL[5:0]
Table 40. SLIC Control Indirect Registers Description
Addr. Description Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hysteresis is enabled (direct Register 108, bit 0). The range is 0-80 mA in 1.27 mA steps. Ring Trip Threshold. Ring trip detection threshold during ringing. Common Mode Minimum Threshold for Speed-Up. This register defines the negative common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0-23.625 V in 0.375 V steps. Common Mode Maximum Threshold for Speed-Up. This register defines the positive common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0-23.625 V in 0.375 V steps. Power Alarm Threshold for Transistors Q1 and Q2. Reference Page
15
28
16 17
38
18
19
27
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Table 40. SLIC Control Indirect Registers Description (Continued)
Addr. Description Power Alarm Threshold for Transistors Q3 and Q4. Power Alarm Threshold for Transistors Q5 and Q6. Loop Closure Filter Coefficient. Ring Trip Filter Coefficient. Thermal Low Pass Filter Pole for Transistors Q1 and Q2. Thermal Low Pass Filter Pole for Transistors Q3 and Q4. Thermal Low Pass Filter Pole for Transistors Q5 and Q6. Common Mode Bias Adjust During Ringing. Recommended value of 0 decimal. DC-DC Converter VOV Voltage. Reference Page
20 21 22 23 24 25 26 27 64
27 27 28 38 27 27 27 35 29
This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter. When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V (VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V (VMIND = 0 to 9h). 66
Loop Closure Threshold--Lower Bound. This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of direct Register 108. The range is 0-80 mA in 1.27 mA steps.
28
4.4. FSK Control
For detailed instructions on FSK signal generation, refer to "AN32: FSK Generation". These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6).
Table 41. FSK Control Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
69 70 71 72 73 74
FSK0X[15:0] FSK0[15:0] FSK1X[15:0] FSK1[15:0] FSK01[15:0] FSK10[15:0]
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Table 42. FSK Control Indirect Registers Description
Addr Description FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. FSK Amplitude Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. FSK Transition Parameter from 0 to 1. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a space (0) to a mark (1). FSK Transition Parameter from 1 to 0. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a mark (1) to a space (0). Reference Page
69
35 and AN32
70
35 and AN32
71
35 and AN32
72
35 and AN32
73
35 and AN32
74
35 and AN32
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Si3215
5. Pin Descriptions: Si3215
QFN
DRX PCLK INT CS SCLK SDI SDO
CS INT PCLK DRX DTX FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC STIPE SVBAT SRINGE
TSSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 SCLK SDI SDO SDITHRU DCDRV DCFF TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP GNDA IGMN SRINGAC STIPAC
DTX FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC
1 38 37 36 35 34 33 32 31 30 2 3 4 5 6 7 8 9 10 11 29 28 27 26 25 24 23 22 21
12 13 14 15 16 17 18 19 20
SDITHRU DCDRV DCFF TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP
Pin # QFN
Pin # TSSOP
Name
STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA
Description Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. Interrupt.
35
1
CS
36 37 38 1 2
2 3 4 5 6
INT PCLK DRX DTX FSYNC
Maskable interrupt output. Open drain output for wire-ORed operation.
PCM Bus Clock.
Clock input for PCM bus timing.
Receive PCM Data.
Input data from PCM bus.
Transmit PCM Data.
Output data to PCM bus.
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format. 3 7 RESET
Reset.
Active low input. Hardware reset used to place all control registers in the default state. 4 8 SDCH
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the converter.
Rev. 0.92
107
Si3215
Pin # QFN Pin # TSSOP Name Description DC Monitor.
5
9
SDCL
DC-DC converter monitor input used to detect overcurrent situations in the converter. 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VDDA1 IREF CAPP QGND CAPM STIPDC
Analog Supply Voltage.
Analog power supply for internal analog circuitry.
Current Reference.
Connects to an external resistor used to provide a high accuracy reference current.
SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
Component Reference Ground. SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
TIP Sense.
Analog current input used to sense voltage on the TIP lead. SRINGDC RING Sense. Analog current input used to sense voltage on the RING lead. STIPE SVBAT
TIP Emitter Sense.
Analog current input used to sense voltage on the Q6 emitter lead.
VBAT Sense.
Analog current input used to sense voltage on dc-dc converter output voltage lead. SRINGE RING Emitter Sense. Analog current input used to sense voltage on the Q5 emitter lead. STIPAC
TIP Transmit Input.
Analog ac input used to detect voltage on the TIP lead. SRINGAC RING Transmit Input. Analog ac input used to detect voltage on the RING lead. IGMN GNDA IGMP IRINGN IRINGP VDDA2
Transconductance Amplifier External Resistor.
Negative connection for transconductance gain setting resistor.
Analog Ground.
Ground connection for internal analog circuitry.
Transconductance Amplifier External Resistor.
Positive connection for transconductance gain setting resistor.
Negative Ring Current Control.
Analog current output driving Q3.
Positive Ring Current Control.
Analog current output driving Q2.
Analog Supply Voltage.
Analog power supply for internal analog circuitry.
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Si3215
Pin # QFN Pin # TSSOP Name Description Positive TIP Current Control.
24 25 26 27 28
28 29 30 31 32
ITIPP ITIPN VDDD GNDD TEST
Analog current output driving Q1.
Negative TIP Current Control.
Analog current output driving Q4.
Digital Supply Voltage.
Digital power supply for internal digital circuitry.
Digital Ground.
Ground connection for internal digital circuitry.
Test.
Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation. 29 33 DCFF
DC Feed-Forward/High Current General Purpose Output.
Feed-forward drive of external bipolar transistors to improve dc-dc converter efficiency. 30 31 32 33 34 34 35 36 37 38 DCDRV
DC Drive/Battery Switch.
DC-DC converter control signal output which drives external bipolar transistor. SDITHRU SDI Passthrough. Cascaded SDI output signal for daisy-chain mode. SDO SDI SCLK
Serial Port Data Out.
Serial port control data output.
Serial Port Data In.
Serial port control data input.
Serial Port Bit Clock Input.
Serial port clock input. Controls the serial data on SDO and latches the data on SDI.
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6. Pin Descriptions: Si3201
TIP NC RING VBAT VBATH NC GND VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ITIPP ITIPN IRINGP IRINGN NC STIPE SRINGE NC
Pin #
Name
Input/ Output
Description TIP Output--Connect to the TIP lead of the subscriber loop. No Internal Connection--Do not connect to any electrical signal. RING Output--Connect to the RING lead of the subscriber loop. Operating Battery Voltage--Connect to the battery supply. High Battery Voltage--This pin is internally connected to VBAT. Ground--Connect to a low impedance ground plane. Supply Voltage--Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply. Decouple locally with a 0.1 F/6 V capacitor. RING Emitter Sense Output--Connect to the SRINGE pin of the Si321x pin. TIP Emitter Sense Output--Connect to the STIPE pin of the Si321x pin. Negative RING Current Control--Connect to the IRINGN lead of the Si321x. Positive RING Current Drive--Connect to the IRINGP lead of the Si321x. Negative TIP Current Control--Connect to the ITIPN lead of the Si321x. Positive TIP Current Control--Connect to the ITIPP lead of the Si321x. Exposed Thermal Pad--Connect to the bulk ground plane.
1 2, 6, 9, 12 3 4 5 7 8 10 11 13 14 15 16
TIP NC RING VBAT VBATH GND VDD SRINGE STIPE IRINGN IRINGP ITIPN ITIPP
I/O -- I/O -- -- -- -- O O I I I I --
Bottom-Side Exposed Pad
110
Rev. 0.92
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7. Ordering Guide
Device Description DCFF Pin Package Lead-Free and RoHS-Compliant Temp Range
Si3215-X-FM Si3215-X-GM Si3215M-X-FM Si3215M-X-GM Si3215-FT Si3215-GT Si3215M-FT Si3215M-GT Si3215-KT SI3215-BT Si3215M-KT Si3215M-BT Si3201-FS Si3201-GS Si3201-KS Si3201-BS
ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC Line Interface Line Interface Line Interface Line Interface
DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV N/A N/A N/A N/A
QFN-38 QFN-38 QFN-38 QFN-38 TSSOP-38 TSSOP-38 TSSOP-38 TSSOP-38 TSSOP-38 TSSOP-38 TSSOP-38 TSSOP-38 SOIC-16 SOIC-16 SOIC-16 SOIC-16
Yes Yes Yes Yes Yes Yes Yes Yes No No No No Yes Yes No No
0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C
Notes: 1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel.
Rev. 0.92
111
Si3215
Table 43. Evaluation Kit Ordering Guide
Item Supported ProSLIC Description Linefeed Interface
Si3215PPQX-EVB Si3215PPQ1-EVB Si3215DCQX-EVB Si3215DCQ1-EVB Si3215MPPQX-EVB Si3215MPPQ1-EVB Si3215MDCQX-EVB Si3215MDCQ1-EVB
Si3215-QFN Si3215-QFN Si3215-QFN Si3215-QFN Si3215M-QFN Si3215M-QFN Si3215M-QFN Si3215M-QFN
Evaluation Board, Daughter Card Evaluation Board, Daughter Card Daughter Card Only Daughter Card Only Evaluation Board, Daughter Card Evaluation Board, Daughter Card Daughter Card Only Daughter Card Only
Discrete Si3201 Discrete Si3201 Discrete Si3201 Discrete Si3201
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8. Package Outline: 38-Pin QFN
Figure 31 illustrates the package details for the Si321x. Table 44 lists the values for the dimensions shown in the illustration.
Bottom Side Exposed Pad 3.2 x 5.2 mm
Figure 31. 38-Pin Quad Flat No-Lead Package (QFN)
Table 44. Package Diagram Dimensions1,2,3
Millimeters Symbol Min Nom Max
A A1 b D D2 e E E2 L L1 aaa bbb ccc ddd
0.75 0.00 0.18 3.10
0.85 0.01 0.23 5.00 BSC. 3.20 0.50 BSC. 7.00 BSC.
0.95 0.05 0.30 3.30
5.10 0.35 0.03 -- -- -- --
5.20 0.45 0.05 -- -- -- --
5.30 0.55 0.08 0.10 0.10 0.08 0.10
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Rev. 0.92
113
Si3215
9. Package Outline: 38-Pin TSSOP
Figure 32 illustrates the package details for the Si321x. Table 45 lists the values for the dimensions shown in the illustration.
B
2x E/2
E1
E L
ddd C B A
2x A D
aaa C
e
ccc
A Seating Plane C 38x
bbb
M
b
CBA
A1 Approximate device weight is 115.7 mg
C
Figure 32. 38-Pin Thin Shrink Small Outline Package (TSSOP)
Table 45. Package Diagram Dimensions
Millimeters Symbol Min Nom Max
A A1 b c D e E E1 L
-- 0.05 0.17 0.09 9.60
-- -- -- -- 9.70 0.50 BSC 6.40 BSC
1.20 0.15 0.27 0.20 9.80
4.30 0.45 0
4.40 0.60 -- 0.10 0.08 0.05 0.20
4.50 0.75 8
aaa bbb ccc ddd
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10. Package Outline: 16-Pin ESOIC
Figure 33 illustrates the package details for the Si3201. Table 46 lists the values for the dimensions shown in the illustration.
16
9 h E H -B- .25 M B M x45
1
B
8
Bottom Side Exposed Pad 2.3 x 3.6 mm
L Detail F
.25 M C A M B S
-A-
D C -C- A See Detail F
e
A1
Seating Plane
Weight: Approximate device weight is 0.15 grams.
Figure 33. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package
Table 46. Package Diagram Dimensions
Millimeters Symbol Min Max
A A1 B C D E e H h L

1.35 0 .33 .19 9.80 3.80 5.80 .25 .40 -- 0
1.75 0.15 .51 .25 10.00 4.00 6.20 .50 1.27 0.10 8
1.27 BSC
Rev. 0.92
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Si3215
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.91
Separated the Si3216/15 document into two data sheets. Added QFN package graphic to cover page. Corrected EVB ordering part numbers.
Revision 0.91 to Revision 0.92
Figure 12, "Si3215/Si3215M Typical Application Circuit Using Discrete Components," on page 20.
Added optional components to application schematic to improve idle channel noise.
"Register 10. Two-Wire Impedance Synthesis Control" on page 59.
Corrected description for China impedance from "(200 + 600 || 100 nF)" to "200 + (680 || 100 nF)".
"7. Ordering Guide" on page 111.
Updated to include product revision designator
Table 43, "Evaluation Kit Ordering Guide," on page 112.
Updated to include "M" version of device.
Table 15, "Si3215/Si3215M External Component Values--Discrete Solution," on page 20.
Added TO-92 transistor suppliers to BOM.
Table 46, "Package Diagram Dimensions," on page 115
Changed A1 max from 0.10 to 0.15.
Rev. C Si3215 Silicon:
Register 14, "Powerdown Control 1," on page 61.
Changed Bit 3 from "Monitor ADC Power-Off Control" to "PLL Free-Run Control".
116
Rev. 0.92
Si3215
NOTES:
Rev. 0.92
117
Si3215
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Rev. 0.92

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